riscv/rocket-chip
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use address map instead of MMIOBase to find size of memory

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This commit is contained in:
Howard Mao
2016-04-21 15:34:28 -07:00
committed by Andrew Waterman
parent 2d6f35525e
commit b7527268bb
4 changed files with 9 additions and 7 deletions
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3
rocket/src/main/scala/csr.scala
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@ -8,6 +8,7 @@ import Instructions._
import cde.{Parameters, Field}
import uncore._
import scala.math._
import junctions.{AddrHashMap, GlobalAddrMap}
class MStatus extends Bundle {
val prv = UInt(width = PRV.SZ) // not truly part of mstatus, but convenient
@ -227,7 +228,7 @@ class CSRFile(implicit p: Parameters) extends CoreModule()(p)
CSRs.misa -> UInt(isa),
CSRs.mstatus -> read_mstatus,
CSRs.mtvec -> reg_mtvec,
CSRs.mcfgaddr -> UInt(p(junctions.MMIOBase)),
CSRs.mcfgaddr -> UInt(addrMap("mem").size),
CSRs.mipi -> reg_mip.msip,
CSRs.mip -> read_mip,
CSRs.mie -> reg_mie,