FrontBus: FIFOFixer should not have a buffer between it and Xbar
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@ -19,25 +19,24 @@ case object FrontBusParams extends Field[FrontBusParams]
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class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
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class FrontBus(params: FrontBusParams)(implicit p: Parameters) extends TLBusWrapper(params, "FrontBus") {
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private val master_buffer = LazyModule(new TLBuffer(params.masterBuffering))
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private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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private val master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.all))
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master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
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inwardBufNode :=* master_fixer.node
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def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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master_buffer.suggestName(s"${busName}_master_TLBuffer")
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val (in, out) = bufferChain(addBuffers, name)
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master_fixer.suggestName(s"${busName}_master_TLFIFOFixer")
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inwardBufNode :=* out
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in
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master_fixer.node :=* master_buffer.node
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}
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inwardNode :=* master_fixer.node
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def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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def fromSyncPorts(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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val (in, out) = bufferChain(addBuffers, name)
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val (in, out) = bufferChain(addBuffers, name)
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master_fixer.node :=* out
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master_buffer.node :=* out
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in
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in
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}
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}
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def fromSyncFIFOMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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def fromSyncMasters(addBuffers: Int = 0, name: Option[String] = None): TLInwardNode = {
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val (in, out) = bufferChain(addBuffers, name)
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val (in, out) = bufferChain(addBuffers, name)
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master_fixer.node :=* out
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master_buffer.node :=* out
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in
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in
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}
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}
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