Merge branch 'master' into ss-frontend
Conflicts: src/main/scala/ctrl.scala
This commit is contained in:
Andrew Waterman
@ -22,11 +22,6 @@ class Datapath extends Module
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// execute definitions
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val ex_reg_pc = Reg(UInt())
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val ex_reg_inst = Reg(Bits())
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val ex_reg_ctrl_fn_dw = Reg(UInt())
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val ex_reg_ctrl_fn_alu = Reg(UInt())
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val ex_reg_sel_alu2 = Reg(UInt())
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val ex_reg_sel_alu1 = Reg(UInt())
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val ex_reg_sel_imm = Reg(UInt())
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val ex_reg_kill = Reg(Bool())
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val ex_reg_rs_bypass = Vec.fill(2)(Reg(Bool()))
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val ex_reg_rs_lsb = Vec.fill(2)(Reg(Bits()))
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@ -102,11 +97,6 @@ class Datapath extends Module
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when (!io.ctrl.killd) {
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ex_reg_pc := id_pc
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ex_reg_inst := id_inst
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ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUInt
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ex_reg_ctrl_fn_alu := io.ctrl.fn_alu
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ex_reg_sel_alu2 := io.ctrl.sel_alu2
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ex_reg_sel_alu1 := io.ctrl.sel_alu1
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ex_reg_sel_imm := io.ctrl.sel_imm
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ex_reg_rs_bypass := io.ctrl.bypass
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for (i <- 0 until id_rs.size) {
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when (io.ctrl.ren(i)) {
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@ -129,31 +119,31 @@ class Datapath extends Module
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val ex_rs = for (i <- 0 until id_rs.size)
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yield Mux(ex_reg_rs_bypass(i), bypass(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i)))
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val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst)
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val ex_op1 = MuxLookup(ex_reg_sel_alu1, SInt(0), Seq(
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val ex_imm = imm(io.ctrl.ex_ctrl.sel_imm, ex_reg_inst)
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val ex_op1 = MuxLookup(io.ctrl.ex_ctrl.sel_alu1, SInt(0), Seq(
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A1_RS1 -> ex_rs(0).toSInt,
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A1_PC -> ex_reg_pc.toSInt))
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val ex_op2 = MuxLookup(ex_reg_sel_alu2, SInt(0), Seq(
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val ex_op2 = MuxLookup(io.ctrl.ex_ctrl.sel_alu2, SInt(0), Seq(
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A2_RS2 -> ex_rs(1).toSInt,
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A2_IMM -> ex_imm,
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A2_FOUR -> SInt(4)))
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val alu = Module(new ALU)
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alu.io.dw := ex_reg_ctrl_fn_dw
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alu.io.fn := ex_reg_ctrl_fn_alu
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alu.io.dw := io.ctrl.ex_ctrl.alu_dw
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alu.io.fn := io.ctrl.ex_ctrl.alu_fn
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alu.io.in2 := ex_op2.toUInt
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alu.io.in1 := ex_op1
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// multiplier and divider
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val div = Module(new MulDiv(mulUnroll = if(params(FastMulDiv)) 8 else 1,
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earlyOut = params(FastMulDiv)))
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div.io.req.valid := io.ctrl.div_mul_val
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div.io.req.bits.dw := ex_reg_ctrl_fn_dw
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div.io.req.bits.fn := ex_reg_ctrl_fn_alu
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div.io.req.valid := io.ctrl.ex_valid && io.ctrl.ex_ctrl.div
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div.io.req.bits.dw := io.ctrl.ex_ctrl.alu_dw
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div.io.req.bits.fn := io.ctrl.ex_ctrl.alu_fn
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div.io.req.bits.in1 := ex_rs(0)
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div.io.req.bits.in2 := ex_rs(1)
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div.io.req.bits.tag := io.ctrl.ex_waddr
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div.io.kill := io.ctrl.div_mul_kill
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div.io.kill := io.ctrl.killm && Reg(next = div.io.req.fire())
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io.ctrl.div_mul_rdy := div.io.req.ready
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io.fpu.fromint_data := ex_rs(0)
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@ -171,7 +161,7 @@ class Datapath extends Module
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// D$ request interface (registered inside D$ module)
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// other signals (req_val, req_rdy) connect to control module
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io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(params(VAddrBits)-1,0)).toUInt
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io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val)
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io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_ctrl.fp)
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require(io.dmem.req.bits.tag.getWidth >= 6)
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require(params(CoreDCacheReqTagBits) >= 6)
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@ -196,12 +186,12 @@ class Datapath extends Module
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mem_reg_pc := ex_reg_pc
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mem_reg_inst := ex_reg_inst
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mem_reg_wdata := alu.io.out
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}
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when (io.ctrl.ex_rs2_val) {
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mem_reg_rs2 := ex_rs(1)
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when (io.ctrl.ex_ctrl.rxs2 && (io.ctrl.ex_ctrl.mem || io.ctrl.ex_ctrl.rocc)) {
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mem_reg_rs2 := ex_rs(1)
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}
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}
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io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2)
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io.dmem.req.bits.data := Mux(io.ctrl.mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2)
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// writeback arbitration
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val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool
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@ -239,21 +229,21 @@ class Datapath extends Module
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io.ctrl.mem_br_taken := mem_reg_wdata(0)
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val mem_br_target = mem_reg_pc +
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Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
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Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4)))
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val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(params(VAddrBits)-1,0)), mem_br_target)
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Mux(io.ctrl.mem_ctrl.branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst),
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Mux(io.ctrl.mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4)))
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val mem_npc = Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(params(VAddrBits)-1,0)), mem_br_target)
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io.ctrl.mem_misprediction := mem_npc != ex_reg_pc || !io.ctrl.ex_valid
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io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1
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val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata)
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val mem_int_wdata = Mux(io.ctrl.mem_ctrl.jalr, mem_br_target, mem_reg_wdata)
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// writeback stage
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when (!mem_reg_kill) {
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wb_reg_pc := mem_reg_pc
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wb_reg_inst := mem_reg_inst
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wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_int_wdata)
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}
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when (io.ctrl.mem_rocc_val) {
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wb_reg_rs2 := mem_reg_rs2
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wb_reg_wdata := Mux(io.ctrl.mem_ctrl.fp && io.ctrl.mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata)
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when (io.ctrl.mem_ctrl.rocc) {
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wb_reg_rs2 := mem_reg_rs2
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}
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}
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wb_wdata := Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword,
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Mux(io.ctrl.ll_wen, ll_wdata,
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