diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 247a12b9..b0561ef5 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -12,33 +12,15 @@ class CtrlDpathIO extends Bundle { // outputs to datapath val sel_pc = UInt(OUTPUT, 3) - val killd = Bool(OUTPUT) + val killd = Bool(OUTPUT) + val killm = Bool(OUTPUT) val ren = Vec.fill(2)(Bool(OUTPUT)) - val sel_alu2 = UInt(OUTPUT, 3) - val sel_alu1 = UInt(OUTPUT, 2) - val sel_imm = UInt(OUTPUT, 3) - val fn_dw = Bool(OUTPUT) - val fn_alu = UInt(OUTPUT, SZ_ALU_FN) - val div_mul_val = Bool(OUTPUT) - val div_mul_kill = Bool(OUTPUT) - val div_val = Bool(OUTPUT) - val div_kill = Bool(OUTPUT) + val ex_ctrl = new IntCtrlSigs().asOutput + val mem_ctrl = new IntCtrlSigs().asOutput val csr = UInt(OUTPUT, 3) val sret = Bool(OUTPUT) - val mem_load = Bool(OUTPUT) - val wb_load = Bool(OUTPUT) - val ex_fp_val= Bool(OUTPUT) - val mem_fp_val= Bool(OUTPUT) - val ex_wen = Bool(OUTPUT) val ex_valid = Bool(OUTPUT) - val mem_jalr = Bool(OUTPUT) - val mem_branch = Bool(OUTPUT) - val mem_wen = Bool(OUTPUT) val wb_wen = Bool(OUTPUT) - val ex_mem_type = Bits(OUTPUT, 3) - val ex_rs2_val = Bool(OUTPUT) - val ex_rocc_val = Bool(OUTPUT) - val mem_rocc_val = Bool(OUTPUT) val bypass = Vec.fill(2)(Bool(OUTPUT)) val bypass_src = Vec.fill(2)(Bits(OUTPUT, SZ_BYP)) val ll_ready = Bool(OUTPUT) @@ -49,7 +31,6 @@ class CtrlDpathIO extends Bundle val badvaddr_wen = Bool(OUTPUT) // high for a load/store access fault // inputs from datapath val inst = Bits(INPUT, 32) - val jalr_eq = Bool(INPUT) val mem_br_taken = Bool(INPUT) val mem_misprediction = Bool(INPUT) val div_mul_rdy = Bool(INPUT) @@ -70,241 +51,281 @@ abstract trait DecodeConstants val xpr64 = Y val decode_default = - // jal fence.i - // | jalr mul_val | sret - // fp_val| | renx2 | div_val | | syscall - // | rocc| | | renx1 s_alu1 mem_val | | wen | | | - // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | | | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - List(N, X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,CSR.X,N,X,X,X,X,X) + // jal renf1 fence.i + // | jalr | renf2 | sret + // fp_val| | renx2 | | renf3 | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | | wfd | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | | div | | | + // | | | | | | | | | | | | | | | | | | | | | wxd | | | fence + // | | | | | | | | | | | | | | | | | | | | | | csr | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | | | + List(N, X,X,X,X,X,X,X,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, X,X,X,X,X,X,CSR.X,X,X,X,X,X) val table: Array[(UInt, List[UInt])] } +class IntCtrlSigs extends Bundle { + val legal = Bool() + val fp = Bool() + val rocc = Bool() + val branch = Bool() + val jal = Bool() + val jalr = Bool() + val rxs2 = Bool() + val rxs1 = Bool() + val sel_alu2 = Bits(width = A2_X.getWidth) + val sel_alu1 = Bits(width = A1_X.getWidth) + val sel_imm = Bits(width = IMM_X.getWidth) + val alu_dw = Bool() + val alu_fn = Bits(width = FN_X.getWidth) + val mem = Bool() + val mem_cmd = Bits(width = M_SZ) + val mem_type = Bits(width = MT_SZ) + val rfs1 = Bool() + val rfs2 = Bool() + val rfs3 = Bool() + val wfd = Bool() + val div = Bool() + val wxd = Bool() + val csr = Bits(width = CSR.SZ) + val fence_i = Bool() + val sret = Bool() + val scall = Bool() + val fence = Bool() + val amo = Bool() + + def decode(inst: UInt, table: Iterable[(UInt, List[UInt])]) = { + val decoder = DecodeLogic(inst, XDecode.decode_default, table) + Vec(legal, fp, rocc, branch, jal, jalr, rxs2, rxs1, sel_alu2, sel_alu1, + sel_imm, alu_dw, alu_fn, mem, mem_cmd, mem_type, + rfs1, rfs2, rfs3, wfd, div, wxd, + csr, fence_i, sret, scall, fence, amo) := decoder + this + } +} + object XDecode extends DecodeConstants { val table = Array( - // jal fence.i - // | jalr mul_val | sret - // fp_val| | renx2 | div_val | | syscall - // | rocc| | | renx1 s_alu1 mem_val | | wen | | | - // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | | | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - BNE-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BEQ-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BLT-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BLTU-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BGE-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - BGEU-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), + // jal renf1 fence.i + // | jalr | renf2 | sret + // fp_val| | renx2 | | renf3 | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | | wfd | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | | div | | | + // | | | | | | | | | | | | | | | | | | | | | wxd | | | fence + // | | | | | | | | | | | | | | | | | | | | | | csr | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | | | + BNE-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SNE, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + BEQ-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SEQ, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + BLT-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLT, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + BLTU-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SLTU, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + BGE-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGE, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + BGEU-> List(Y, N,N,Y,N,N,Y,Y,A2_RS2, A1_RS1, IMM_SB,DW_X, FN_SGEU, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), - JAL-> List(Y, N,N,N,Y,N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - JALR-> List(Y, N,N,N,N,Y,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - AUIPC-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + JAL-> List(Y, N,N,N,Y,N,N,N,A2_FOUR,A1_PC, IMM_UJ,DW_X, FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + JALR-> List(Y, N,N,N,N,Y,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + AUIPC-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_PC, IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), - LB-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,Y,CSR.N,N,N,N,N,N,N), - LH-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,Y,CSR.N,N,N,N,N,N,N), - LW-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,N), - LD-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,N), - LBU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,Y,CSR.N,N,N,N,N,N,N), - LHU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,Y,CSR.N,N,N,N,N,N,N), - LWU-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,Y,CSR.N,N,N,N,N,N,N), - SB-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,CSR.N,N,N,N,N,N,N), - SH-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,CSR.N,N,N,N,N,N,N), - SW-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), - SD-> List(xpr64,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N), + LB-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_B, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + LH-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_H, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + LW-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + LD-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + LBU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_BU,N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + LHU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_HU,N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + LWU-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_WU,N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SB-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_B, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + SH-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_H, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + SW-> List(Y, N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + SD-> List(xpr64,N,N,N,N,N,Y,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,N,N,N,CSR.N,N,N,N,N,N), - AMOADD_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOXOR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOSWAP_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOAND_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOOR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMIN_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMINU_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAX_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAXU_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOADD_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOSWAP_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOXOR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOAND_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOOR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMIN_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMINU_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAX_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - AMOMAXU_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + AMOADD_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOXOR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOSWAP_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOAND_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOOR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMIN_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMINU_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMAX_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMAXU_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOADD_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_ADD, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOSWAP_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_SWAP,MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOXOR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_XOR, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOAND_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_AND, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOOR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_OR, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMIN_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MIN, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMINU_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MINU,MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMAX_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAX, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + AMOMAXU_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XA_MAXU,MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), - LR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - LR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), - SC_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,Y,CSR.N,N,N,N,N,N,Y), - SC_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,Y,CSR.N,N,N,N,N,N,Y), + LR_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + LR_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XLR, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + SC_W-> List(Y, N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_W, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), + SC_D-> List(xpr64,N,N,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, Y,M_XSC, MT_D, N,N,N,N,N,Y,CSR.N,N,N,N,N,Y), - LUI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADDI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLTI -> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLTIU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ANDI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ORI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - XORI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLLI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRLI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRAI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADD-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SUB-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLT-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLTU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - AND-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - OR-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - XOR-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRA-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + LUI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_U, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + ADDI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLTI -> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLTIU-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + ANDI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_AND, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + ORI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_OR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + XORI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLLI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRLI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRAI-> List(Y, N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + ADD-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SUB-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SUB, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLT-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLT, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLTU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SLTU, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + AND-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_AND, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + OR-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_OR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + XOR-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_XOR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SL, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRA-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_SRA, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), - ADDIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLLIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRLIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRAIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - ADDW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SUBW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SLLW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRLW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - SRAW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), + ADDIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLLIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SL, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRLIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRAIW-> List(xpr64,N,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_32,FN_SRA, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + ADDW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SUBW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SUB, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SLLW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SL, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRLW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SR, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + SRAW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32,FN_SRA, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), - MUL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULH-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULHU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULHSU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), - MULW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, Y,N,Y,CSR.N,N,N,N,N,N,N), + MUL-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MUL, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + MULH-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULH, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + MULHU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHU, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + MULHSU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_MULHSU,N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + MULW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_MUL, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), - DIV-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - DIVU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REM-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REMU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - DIVW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - DIVUW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REMW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), - REMUW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,Y,Y,CSR.N,N,N,N,N,N,N), + DIV-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIV, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + DIVU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_DIVU, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + REM-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REM, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + REMU-> List(Y, N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_XPR,FN_REMU, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + DIVW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIV, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + DIVUW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_DIVU, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + REMW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REM, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), + REMUW-> List(xpr64,N,N,N,N,N,Y,Y,A2_RS2, A1_RS1, IMM_X, DW_32, FN_REMU, N,M_X, MT_X, N,N,N,N,Y,Y,CSR.N,N,N,N,N,N), - SCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,Y,N,N,N), - SRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,Y,N,N,N,N), - FENCE-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,Y,N), - FENCE_I-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,Y,N,N,Y,N,N), - CSRRW-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N), - CSRRS-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N), - CSRRC-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N), - CSRRWI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.W,N,N,N,N,N,N), - CSRRSI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.S,N,N,N,N,N,N), - CSRRCI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.C,N,N,N,N,N,N)) + SCALL-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,Y,N,N), + SRET-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,Y,N,N,N), + FENCE-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,Y,N), + FENCE_I-> List(Y, N,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,Y,N,N,N,N), + CSRRW-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.W,N,N,N,N,N), + CSRRS-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.S,N,N,N,N,N), + CSRRC-> List(Y, N,N,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.C,N,N,N,N,N), + CSRRWI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.W,N,N,N,N,N), + CSRRSI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.S,N,N,N,N,N), + CSRRCI-> List(Y, N,N,N,N,N,N,N,A2_IMM, A1_ZERO,IMM_Z, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.C,N,N,N,N,N)) } object FDecode extends DecodeConstants { val table = Array( - // jal fence.i - // | jalr mul_val | sret - // fp_val| | renx2 | div_val | | syscall - // | rocc| | | renx1 s_alu1 mem_val | | wen | | | - // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | | | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - FCVT_S_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJ_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJ_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJX_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJX_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJN_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSGNJN_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMIN_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMIN_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMAX_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMAX_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMUL_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMUL_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FNMSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCLASS_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCLASS_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FMV_X_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FMV_X_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_W_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_W_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_WU_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_WU_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_L_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_L_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_LU_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FCVT_LU_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FEQ_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FEQ_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLT_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLT_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLE_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FLE_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - FMV_S_X-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FMV_D_X-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_W-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_W-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_WU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_WU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_L-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_L-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_S_LU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FCVT_D_LU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - FLW-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), - FLD-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,CSR.N,N,N,N,N,N,N), - FSW-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,N,N,CSR.N,N,N,N,N,N,N), - FSD-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,N,N,CSR.N,N,N,N,N,N,N)) + // jal renf1 fence.i + // | jalr | renf2 | sret + // fp_val| | renx2 | | renf3 | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | | wfd | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | | div | | | + // | | | | | | | | | | | | | | | | | | | | | wxd | | | fence + // | | | | | | | | | | | | | | | | | | | | | | csr | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | | | + FCVT_S_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_D_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FSGNJ_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSGNJ_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSGNJX_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSGNJX_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSGNJN_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSGNJN_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMIN_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMIN_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMAX_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMAX_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMUL_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMUL_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,Y,N,N,CSR.N,N,N,N,N,N), + FMADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FMADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FMSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FMSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FNMADD_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FNMADD_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FNMSUB_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FNMSUB_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,Y,Y,N,N,CSR.N,N,N,N,N,N), + FCLASS_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCLASS_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FMV_X_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FMV_X_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_W_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_W_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_WU_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_WU_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_L_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_L_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_LU_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FCVT_LU_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,N,N,N,N,Y,CSR.N,N,N,N,N,N), + FEQ_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N,N,N), + FEQ_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N,N,N), + FLT_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N,N,N), + FLT_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N,N,N), + FLE_S-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N,N,N), + FLE_D-> List(Y, Y,N,N,N,N,N,N,A2_X, A1_X, IMM_X, DW_X, FN_X, N,M_X, MT_X, Y,Y,N,N,N,Y,CSR.N,N,N,N,N,N), + FMV_S_X-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FMV_D_X-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_S_W-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_D_W-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_S_WU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_D_WU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_S_L-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_D_L-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_S_LU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FCVT_D_LU-> List(Y, Y,N,N,N,N,N,Y,A2_X, A1_RS1, IMM_X, DW_X, FN_X, N,M_X, MT_X, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FLW-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_W, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FLD-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_I, DW_XPR,FN_ADD, Y,M_XRD, MT_D, N,N,N,Y,N,N,CSR.N,N,N,N,N,N), + FSW-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_W, N,Y,N,N,N,N,CSR.N,N,N,N,N,N), + FSD-> List(Y, Y,N,N,N,N,N,Y,A2_IMM, A1_RS1, IMM_S, DW_XPR,FN_ADD, Y,M_XWR, MT_D, N,Y,N,N,N,N,CSR.N,N,N,N,N,N)) } object RoCCDecode extends DecodeConstants { val table = Array( - // jal fence.i - // | jalr mul_val | sret - // fp_val| | renx2 | div_val | | syscall - // | rocc| | | renx1 s_alu1 mem_val | | wen | | | - // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | csr | | | replay_next - // | | | | | | | | | | | | | | | | | | | | | | | | fence - // | | | | | | | | | | | | | | | | | | | | | | | | | amo - // | | | | | | | | | | | | | | | | | | | | | | | | | | - CUSTOM0-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM0_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM0_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM0_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM0_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM0_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM1-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM1_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM1_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM1_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM1_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM1_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM2-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM2_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM2_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM2_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM2_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM2_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM3-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM3_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM3_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,CSR.N,N,N,N,N,N,N), - CUSTOM3_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM3_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N), - CUSTOM3_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,Y,CSR.N,N,N,N,N,N,N)) + // jal renf1 fence.i + // | jalr | renf2 | sret + // fp_val| | renx2 | | renf3 | | syscall + // | rocc| | | renx1 s_alu1 mem_val | | | wfd | | | + // val | | br| | | | s_alu2 | imm dw alu | mem_cmd mem_type| | | | div | | | + // | | | | | | | | | | | | | | | | | | | | | wxd | | | fence + // | | | | | | | | | | | | | | | | | | | | | | csr | | | | amo + // | | | | | | | | | | | | | | | | | | | | | | | | | | | | + CUSTOM0-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM0_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM0_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM0_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM0_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM0_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM1-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM1_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM1_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM1_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM1_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM1_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM2-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM2_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM2_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM2_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM2_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM2_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM3-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM3_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM3_RS1_RS2-> List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,N,CSR.N,N,N,N,N,N), + CUSTOM3_RD-> List(Y, N,Y,N,N,N,N,N,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM3_RD_RS1-> List(Y, N,Y,N,N,N,N,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N), + CUSTOM3_RD_RS1_RS2->List(Y, N,Y,N,N,N,Y,Y,A2_ZERO,A1_RS1, IMM_X, DW_XPR,FN_ADD, N,M_X, MT_X, N,N,N,N,N,Y,CSR.N,N,N,N,N,N)) } class Control extends Module @@ -321,74 +342,38 @@ class Control extends Module if (!params(BuildFPU).isEmpty) decode_table ++= FDecode.table if (!params(BuildRoCC).isEmpty) decode_table ++= RoCCDecode.table - val cs = DecodeLogic(io.dpath.inst, XDecode.decode_default, decode_table) - - val (id_int_val: Bool) :: (id_fp_val: Bool) :: (id_rocc_val: Bool) :: (id_branch: Bool) :: (id_jal: Bool) :: (id_jalr: Bool) :: (id_renx2: Bool) :: (id_renx1: Bool) :: cs0 = cs - val id_sel_alu2 :: id_sel_alu1 :: id_sel_imm :: (id_fn_dw: Bool) :: id_fn_alu :: cs1 = cs0 - val (id_mem_val: Bool) :: id_mem_cmd :: id_mem_type :: (id_mul_val: Bool) :: (id_div_val: Bool) :: (id_wen: Bool) :: cs2 = cs1 - val id_csr :: (id_fence_i: Bool) :: (id_sret: Bool) :: (id_syscall: Bool) :: (id_replay_next: Bool) :: (id_fence: Bool) :: (id_amo: Bool) :: Nil = cs2 + val id_ctrl = new IntCtrlSigs().decode(io.dpath.inst, decode_table) + val ex_ctrl = Reg(new IntCtrlSigs) + val mem_ctrl = Reg(new IntCtrlSigs) + val wb_ctrl = Reg(new IntCtrlSigs) val ex_reg_xcpt_interrupt = Reg(Bool()) val ex_reg_valid = Reg(Bool()) - val ex_reg_branch = Reg(Bool()) - val ex_reg_jal = Reg(Bool()) - val ex_reg_jalr = Reg(Bool()) val ex_reg_btb_hit = Reg(Bool()) val ex_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone) - val ex_reg_sret = Reg(Bool()) - val ex_reg_wen = Reg(Bool()) - val ex_reg_fp_wen = Reg(Bool()) - val ex_reg_flush_inst = Reg(Bool()) - val ex_reg_div_mul_val = Reg(Bool()) - val ex_reg_mem_val = Reg(Bool()) val ex_reg_xcpt = Reg(Bool()) - val ex_reg_fp_val = Reg(Bool()) - val ex_reg_rocc_val = Reg(Bool()) - val ex_reg_replay_next = Reg(Bool()) + val ex_reg_flush_pipe = Reg(Bool()) val ex_reg_load_use = Reg(Bool()) - val ex_reg_csr = Reg(UInt()) - val ex_reg_mem_cmd = Reg(Bits()) - val ex_reg_mem_type = Reg(Bits()) val ex_reg_cause = Reg(UInt()) val mem_reg_xcpt_interrupt = Reg(Bool()) val mem_reg_valid = Reg(Bool()) - val mem_reg_branch = Reg(Bool()) - val mem_reg_jal = Reg(Bool()) - val mem_reg_jalr = Reg(Bool()) val mem_reg_btb_hit = Reg(Bool()) val mem_reg_btb_resp = Reg(io.imem.btb_resp.bits.clone) - val mem_reg_sret = Reg(Bool()) - val mem_reg_wen = Reg(Bool()) - val mem_reg_fp_wen = Reg(Bool()) - val mem_reg_flush_inst = Reg(Bool()) - val mem_reg_div_mul_val = Reg(Bool()) - val mem_reg_mem_val = Reg(Bool()) val mem_reg_xcpt = Reg(Bool()) - val mem_reg_fp_val = Reg(Bool()) - val mem_reg_rocc_val = Reg(Bool()) val mem_reg_replay = Reg(Bool()) - val mem_reg_replay_next = Reg(Bool()) - val mem_reg_csr = Reg(UInt()) + val mem_reg_flush_pipe = Reg(Bool()) val mem_reg_cause = Reg(UInt()) val mem_reg_slow_bypass = Reg(Bool()) val wb_reg_valid = Reg(Bool()) - val wb_reg_csr = Reg(UInt()) - val wb_reg_wen = Reg(Bool()) - val wb_reg_fp_wen = Reg(Bool()) - val wb_reg_rocc_val = Reg(Bool()) - val wb_reg_flush_inst = Reg(Bool()) - val wb_reg_mem_val = Reg(Bool()) - val wb_reg_sret = Reg(Bool()) val wb_reg_xcpt = Reg(Bool()) val wb_reg_replay = Reg(Bool()) val wb_reg_cause = Reg(UInt()) - val wb_reg_fp_val = Reg(Bool()) - val wb_reg_div_mul_val = Reg(Bool()) val take_pc_wb = Bool() - val take_pc_mem = io.dpath.mem_misprediction && (mem_reg_branch || mem_reg_jalr || mem_reg_jal) + val mem_misprediction = io.dpath.mem_misprediction && mem_reg_valid && (mem_ctrl.branch || mem_ctrl.jalr || mem_ctrl.jal) + val take_pc_mem = mem_reg_valid && (mem_misprediction || mem_reg_flush_pipe) val take_pc_mem_wb = take_pc_wb || take_pc_mem val take_pc = take_pc_mem_wb val ctrl_killd = Bool() @@ -418,9 +403,9 @@ class Control extends Module val id_csr_addr = io.dpath.inst(31,20) val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i)) - val id_csr_en = id_csr != CSR.N + val id_csr_en = id_ctrl.csr != CSR.N val id_csr_fp = Bool(!params(BuildFPU).isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) - val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr) + val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_ctrl.csr) val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr) val id_csr_privileged = id_csr_en && (id_csr_addr(11,10) === UInt(3) && id_csr_wen || @@ -437,172 +422,93 @@ class Control extends Module // stall decode for fences (now, for AMO.aq; later, for AMO.rl and FENCE) val id_amo_aq = io.dpath.inst(26) val id_amo_rl = io.dpath.inst(25) - val id_fence_next = id_fence || id_amo && id_amo_rl - val id_mem_busy = !io.dmem.ordered || ex_reg_mem_val + val id_fence_next = id_ctrl.fence || id_ctrl.amo && id_amo_rl + val id_mem_busy = !io.dmem.ordered || io.dmem.req.valid val id_rocc_busy = Bool(!params(BuildRoCC).isEmpty) && - (io.rocc.busy || ex_reg_rocc_val || mem_reg_rocc_val || wb_reg_rocc_val) + (io.rocc.busy || ex_reg_valid && ex_ctrl.rocc || + mem_reg_valid && mem_ctrl.rocc || wb_reg_valid && wb_ctrl.rocc) id_reg_fence := id_fence_next || id_reg_fence && id_mem_busy - val id_do_fence = id_rocc_busy && id_fence || - id_mem_busy && (id_amo && id_amo_aq || id_fence_i || id_reg_fence && (id_mem_val || id_rocc_val) || id_csr_flush) + val id_do_fence = id_rocc_busy && id_ctrl.fence || + id_mem_busy && (id_ctrl.amo && id_amo_aq || id_ctrl.fence_i || id_reg_fence && (id_ctrl.mem || id_ctrl.rocc) || id_csr_flush) val (id_xcpt, id_cause) = checkExceptions(List( (id_interrupt, id_interrupt_cause), (io.imem.resp.bits.xcpt_ma, UInt(Causes.misaligned_fetch)), (io.imem.resp.bits.xcpt_if, UInt(Causes.fault_fetch)), - (!id_int_val || id_csr_invalid, UInt(Causes.illegal_instruction)), + (!id_ctrl.legal || id_csr_invalid, UInt(Causes.illegal_instruction)), (id_csr_privileged, UInt(Causes.privileged_instruction)), - (id_sret && !io.dpath.status.s, UInt(Causes.privileged_instruction)), - ((id_fp_val || id_csr_fp) && !io.dpath.status.ef, UInt(Causes.fp_disabled)), - (id_syscall, UInt(Causes.syscall)), - (id_rocc_val && !io.dpath.status.er, UInt(Causes.accelerator_disabled)))) + (id_ctrl.sret && !io.dpath.status.s, UInt(Causes.privileged_instruction)), + ((id_ctrl.fp || id_csr_fp) && !io.dpath.status.ef,UInt(Causes.fp_disabled)), + (id_ctrl.scall, UInt(Causes.syscall)), + (id_ctrl.rocc && !io.dpath.status.er, UInt(Causes.accelerator_disabled)))) + ex_reg_valid := !ctrl_killd + ex_reg_xcpt := !ctrl_killd && id_xcpt ex_reg_xcpt_interrupt := id_interrupt && !take_pc && io.imem.resp.valid when (id_xcpt) { ex_reg_cause := id_cause } - when (ctrl_killd) { - ex_reg_branch := false - ex_reg_jal := false - ex_reg_jalr := false - ex_reg_btb_hit := false - ex_reg_div_mul_val := Bool(false) - ex_reg_mem_val := Bool(false) - ex_reg_valid := Bool(false) - ex_reg_wen := Bool(false) - ex_reg_fp_wen := Bool(false) - ex_reg_sret := Bool(false) - ex_reg_flush_inst := Bool(false) - ex_reg_fp_val := Bool(false) - ex_reg_rocc_val := Bool(false) - ex_reg_replay_next := Bool(false) - ex_reg_load_use := Bool(false) - ex_reg_csr := CSR.N - ex_reg_xcpt := Bool(false) - } - .otherwise { - ex_reg_branch := id_branch - ex_reg_jal := id_jal - ex_reg_jalr := id_jalr + when (!ctrl_killd) { + ex_ctrl := id_ctrl ex_reg_btb_hit := io.imem.btb_resp.valid when (io.imem.btb_resp.valid) { ex_reg_btb_resp := io.imem.btb_resp.bits } - ex_reg_div_mul_val := id_mul_val || id_div_val - ex_reg_mem_val := id_mem_val.toBool - ex_reg_valid := Bool(true) - ex_reg_csr := id_csr - ex_reg_wen := id_wen - ex_reg_fp_wen := id_fp_val && io.fpu.dec.wen - ex_reg_sret := id_sret - ex_reg_flush_inst := id_fence_i - ex_reg_fp_val := id_fp_val - ex_reg_rocc_val := id_rocc_val.toBool - ex_reg_replay_next := id_replay_next || id_csr_flush + ex_reg_flush_pipe := id_ctrl.fence_i || id_csr_flush ex_reg_load_use := id_load_use - ex_reg_mem_cmd := id_mem_cmd - ex_reg_mem_type := id_mem_type.toUInt ex_reg_xcpt := id_xcpt } // replay inst in ex stage - val wb_dcache_miss = wb_reg_mem_val && !io.dmem.resp.valid - val replay_ex_structural = ex_reg_mem_val && !io.dmem.req.ready || - ex_reg_div_mul_val && !io.dpath.div_mul_rdy - val replay_ex_other = wb_dcache_miss && ex_reg_load_use || mem_reg_replay_next - val replay_ex = replay_ex_structural || replay_ex_other - ctrl_killx := take_pc_mem_wb || replay_ex + val wb_dcache_miss = wb_ctrl.mem && !io.dmem.resp.valid + val replay_ex_structural = ex_ctrl.mem && !io.dmem.req.ready || + ex_ctrl.div && !io.dpath.div_mul_rdy + val replay_ex_load_use = wb_dcache_miss && ex_reg_load_use + val replay_ex = ex_reg_valid && (replay_ex_structural || replay_ex_load_use) + ctrl_killx := take_pc_mem_wb || replay_ex || !ex_reg_valid // detect 2-cycle load-use delay for LB/LH/SC - val ex_slow_bypass = ex_reg_mem_cmd === M_XSC || Vec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_reg_mem_type) + val ex_slow_bypass = ex_ctrl.mem_cmd === M_XSC || Vec(MT_B, MT_BU, MT_H, MT_HU).contains(ex_ctrl.mem_type) val (ex_xcpt, ex_cause) = checkExceptions(List( (ex_reg_xcpt_interrupt || ex_reg_xcpt, ex_reg_cause), - (ex_reg_fp_val && io.fpu.illegal_rm, UInt(Causes.illegal_instruction)))) + (ex_ctrl.fp && io.fpu.illegal_rm, UInt(Causes.illegal_instruction)))) + mem_reg_valid := !ctrl_killx mem_reg_replay := !take_pc_mem_wb && replay_ex - mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt && !mem_reg_replay_next + mem_reg_xcpt := !ctrl_killx && ex_xcpt + mem_reg_xcpt_interrupt := !take_pc_mem_wb && ex_reg_xcpt_interrupt when (ex_xcpt) { mem_reg_cause := ex_cause } - mem_reg_div_mul_val := ex_reg_div_mul_val && io.dpath.div_mul_rdy - when (ctrl_killx) { - mem_reg_valid := false - mem_reg_branch := false - mem_reg_jal := false - mem_reg_jalr := false - mem_reg_csr := CSR.N - mem_reg_wen := Bool(false) - mem_reg_fp_wen := Bool(false) - mem_reg_sret := Bool(false) - mem_reg_mem_val := Bool(false) - mem_reg_flush_inst := Bool(false) - mem_reg_fp_val := Bool(false) - mem_reg_rocc_val := Bool(false) - mem_reg_replay_next := Bool(false) - mem_reg_xcpt := Bool(false) - } - .otherwise { - mem_reg_valid := ex_reg_valid - mem_reg_branch := ex_reg_branch - mem_reg_jal := ex_reg_jal - mem_reg_jalr := ex_reg_jalr + when (!ctrl_killx) { + mem_ctrl := ex_ctrl mem_reg_btb_hit := ex_reg_btb_hit when (ex_reg_btb_hit) { mem_reg_btb_resp := ex_reg_btb_resp } - mem_reg_csr := ex_reg_csr - mem_reg_wen := ex_reg_wen - mem_reg_fp_wen := ex_reg_fp_wen - mem_reg_sret := ex_reg_sret - mem_reg_mem_val := ex_reg_mem_val - mem_reg_flush_inst := ex_reg_flush_inst - mem_reg_fp_val := ex_reg_fp_val - mem_reg_rocc_val := ex_reg_rocc_val - mem_reg_replay_next := ex_reg_replay_next + mem_reg_flush_pipe := ex_reg_flush_pipe mem_reg_slow_bypass := ex_slow_bypass mem_reg_xcpt := ex_xcpt } val (mem_xcpt, mem_cause) = checkExceptions(List( - (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), - (mem_reg_mem_val && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)), - (mem_reg_mem_val && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)), - (mem_reg_mem_val && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load)), - (mem_reg_mem_val && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)))) + (mem_reg_xcpt_interrupt || mem_reg_xcpt, mem_reg_cause), + (mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.ma.st, UInt(Causes.misaligned_store)), + (mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.ma.ld, UInt(Causes.misaligned_load)), + (mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.pf.st, UInt(Causes.fault_store)), + (mem_reg_valid && mem_ctrl.mem && io.dmem.xcpt.pf.ld, UInt(Causes.fault_load)))) - val dcache_kill_mem = mem_reg_wen && io.dmem.replay_next.valid // structural hazard on writeback port - val fpu_kill_mem = mem_reg_fp_val && io.fpu.nack_mem + val dcache_kill_mem = mem_reg_valid && mem_ctrl.wxd && io.dmem.replay_next.valid // structural hazard on writeback port + val fpu_kill_mem = mem_reg_valid && mem_ctrl.fp && io.fpu.nack_mem val replay_mem = dcache_kill_mem || mem_reg_replay || fpu_kill_mem val killm_common = dcache_kill_mem || take_pc_wb || mem_reg_xcpt || !mem_reg_valid ctrl_killm := killm_common || mem_xcpt || fpu_kill_mem + wb_reg_valid := !ctrl_killm + when (!ctrl_killm) { wb_ctrl := mem_ctrl } wb_reg_replay := replay_mem && !take_pc_wb wb_reg_xcpt := mem_xcpt && !take_pc_wb when (mem_xcpt) { wb_reg_cause := mem_cause } - when (ctrl_killm) { - wb_reg_valid := Bool(false) - wb_reg_csr := CSR.N - wb_reg_wen := Bool(false) - wb_reg_fp_wen := Bool(false) - wb_reg_sret := Bool(false) - wb_reg_flush_inst := Bool(false) - wb_reg_mem_val := Bool(false) - wb_reg_div_mul_val := Bool(false) - wb_reg_fp_val := Bool(false) - wb_reg_rocc_val := Bool(false) - } - .otherwise { - wb_reg_valid := mem_reg_valid - wb_reg_csr := mem_reg_csr - wb_reg_wen := mem_reg_wen - wb_reg_fp_wen := mem_reg_fp_wen - wb_reg_sret := mem_reg_sret && !mem_reg_replay - wb_reg_flush_inst := mem_reg_flush_inst - wb_reg_mem_val := mem_reg_mem_val - wb_reg_div_mul_val := mem_reg_div_mul_val - wb_reg_fp_val := mem_reg_fp_val - wb_reg_rocc_val := mem_reg_rocc_val - } - - val wb_set_sboard = wb_reg_div_mul_val || wb_dcache_miss || wb_reg_rocc_val + val wb_set_sboard = wb_ctrl.div || wb_dcache_miss || wb_ctrl.rocc val replay_wb_common = io.dmem.resp.bits.nack || wb_reg_replay || io.dpath.csr_replay - val wb_rocc_val = wb_reg_rocc_val && !replay_wb_common - val replay_wb = replay_wb_common || wb_reg_rocc_val && !io.rocc.cmd.ready + val wb_rocc_val = wb_reg_valid && wb_ctrl.rocc && !replay_wb_common + val replay_wb = replay_wb_common || wb_reg_valid && wb_ctrl.rocc && !io.rocc.cmd.ready class Scoreboard(n: Int) { @@ -627,7 +533,7 @@ class Control extends Module val id_stall_fpu = if (!params(BuildFPU).isEmpty) { val fp_sboard = new Scoreboard(32) - fp_sboard.set((wb_dcache_miss && wb_reg_fp_wen || io.fpu.sboard_set) && !replay_wb, io.dpath.wb_waddr) + fp_sboard.set((wb_dcache_miss && wb_ctrl.wfd || io.fpu.sboard_set) && io.dpath.retire, io.dpath.wb_waddr) fp_sboard.clear(io.dpath.fp_sboard_clr, io.dpath.fp_sboard_clra) fp_sboard.clear(io.fpu.sboard_clr, io.fpu.sboard_clra) @@ -644,29 +550,29 @@ class Control extends Module io.dpath.badvaddr_wen := wb_reg_xcpt // don't care for non-memory exceptions // control transfer from ex/wb - take_pc_wb := replay_wb || wb_reg_xcpt || wb_reg_sret + take_pc_wb := replay_wb || wb_reg_xcpt || io.dpath.sret io.dpath.sel_pc := - Mux(wb_reg_xcpt, PC_PCR, // exception - Mux(wb_reg_sret, PC_PCR, // sret instruction - Mux(replay_wb, PC_WB, // replay - PC_MEM))) + Mux(wb_reg_xcpt, PC_PCR, // exception + Mux(replay_wb, PC_WB, // replay + Mux(wb_reg_valid && wb_ctrl.sret, PC_PCR, // sret instruction + PC_MEM))) - io.imem.btb_update.valid := io.dpath.mem_misprediction && ((mem_reg_branch && io.dpath.mem_br_taken) || mem_reg_jalr || mem_reg_jal) && !take_pc_wb + io.imem.btb_update.valid := io.dpath.mem_misprediction && ((mem_ctrl.branch && io.dpath.mem_br_taken) || mem_ctrl.jalr || mem_ctrl.jal) && !take_pc_wb io.imem.btb_update.bits.prediction.valid := mem_reg_btb_hit io.imem.btb_update.bits.prediction.bits := mem_reg_btb_resp - io.imem.btb_update.bits.isJump := mem_reg_jal || mem_reg_jalr - io.imem.btb_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra + io.imem.btb_update.bits.isJump := mem_ctrl.jal || mem_ctrl.jalr + io.imem.btb_update.bits.isReturn := mem_ctrl.jalr && io.dpath.mem_rs1_ra - io.imem.bht_update.valid := mem_reg_branch && !take_pc_wb + io.imem.bht_update.valid := mem_reg_valid && mem_ctrl.branch && !take_pc_wb io.imem.bht_update.bits.taken := io.dpath.mem_br_taken io.imem.bht_update.bits.mispredict := io.dpath.mem_misprediction io.imem.bht_update.bits.prediction.valid := mem_reg_btb_hit io.imem.bht_update.bits.prediction.bits := mem_reg_btb_resp io.imem.ras_update.valid := io.imem.btb_update.bits.isJump && !take_pc_wb - io.imem.ras_update.bits.isCall := mem_reg_wen && io.dpath.mem_waddr(0) - io.imem.ras_update.bits.isReturn := mem_reg_jalr && io.dpath.mem_rs1_ra + io.imem.ras_update.bits.isCall := mem_ctrl.wen && io.dpath.mem_waddr(0) + io.imem.ras_update.bits.isReturn := mem_ctrl.jalr && io.dpath.mem_rs1_ra io.imem.ras_update.bits.prediction.valid := mem_reg_btb_hit io.imem.ras_update.bits.prediction.bits := mem_reg_btb_resp @@ -674,9 +580,9 @@ class Control extends Module val bypassDst = Array(id_raddr1, id_raddr2) val bypassSrc = Array.fill(NBYP)((Bool(true), UInt(0))) - bypassSrc(BYP_EX) = (ex_reg_wen, io.dpath.ex_waddr) - bypassSrc(BYP_MEM) = (mem_reg_wen && !mem_reg_mem_val, io.dpath.mem_waddr) - bypassSrc(BYP_DC) = (mem_reg_wen, io.dpath.mem_waddr) + bypassSrc(BYP_EX) = (ex_reg_valid && ex_ctrl.wxd, io.dpath.ex_waddr) + bypassSrc(BYP_MEM) = (mem_reg_valid && mem_ctrl.wxd && !mem_ctrl.mem, io.dpath.mem_waddr) + bypassSrc(BYP_DC) = (mem_reg_valid && mem_ctrl.wxd, io.dpath.mem_waddr) val doBypass = bypassDst.map(d => bypassSrc.map(s => s._1 && s._2 === d)) for (i <- 0 until io.dpath.bypass.size) { @@ -685,50 +591,49 @@ class Control extends Module } // stall for RAW/WAW hazards on PCRs, loads, AMOs, and mul/div in execute stage. - val id_renx1_not0 = id_renx1 && id_raddr1 != UInt(0) - val id_renx2_not0 = id_renx2 && id_raddr2 != UInt(0) - val id_wen_not0 = id_wen && id_waddr != UInt(0) - val data_hazard_ex = ex_reg_wen && + val id_renx1_not0 = id_ctrl.rxs1 && id_raddr1 != UInt(0) + val id_renx2_not0 = id_ctrl.rxs2 && id_raddr2 != UInt(0) + val id_wen_not0 = id_ctrl.wxd && id_waddr != UInt(0) + val ex_cannot_bypass = ex_ctrl.csr != CSR.N || ex_ctrl.jalr || ex_ctrl.mem || ex_ctrl.div || ex_ctrl.fp || ex_ctrl.rocc + val data_hazard_ex = ex_ctrl.wxd && (id_renx1_not0 && id_raddr1 === io.dpath.ex_waddr || id_renx2_not0 && id_raddr2 === io.dpath.ex_waddr || id_wen_not0 && id_waddr === io.dpath.ex_waddr) - val fp_data_hazard_ex = ex_reg_fp_wen && + val fp_data_hazard_ex = ex_ctrl.wfd && (io.fpu.dec.ren1 && id_raddr1 === io.dpath.ex_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.ex_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.ex_waddr || io.fpu.dec.wen && id_waddr === io.dpath.ex_waddr) - val id_ex_hazard = data_hazard_ex && (ex_reg_csr != CSR.N || ex_reg_jalr || ex_reg_mem_val || ex_reg_div_mul_val || ex_reg_fp_val || ex_reg_rocc_val) || - fp_data_hazard_ex && (ex_reg_mem_val || ex_reg_fp_val) + val id_ex_hazard = ex_reg_valid && (data_hazard_ex && ex_cannot_bypass || fp_data_hazard_ex) // stall for RAW/WAW hazards on PCRs, LB/LH, and mul/div in memory stage. val mem_mem_cmd_bh = if (params(FastLoadWord)) Bool(!params(FastLoadByte)) && mem_reg_slow_bypass else Bool(true) - val data_hazard_mem = mem_reg_wen && + val mem_cannot_bypass = mem_ctrl.csr != CSR.N || mem_ctrl.mem && mem_mem_cmd_bh || mem_ctrl.div || mem_ctrl.fp || mem_ctrl.rocc + val data_hazard_mem = mem_ctrl.wxd && (id_renx1_not0 && id_raddr1 === io.dpath.mem_waddr || id_renx2_not0 && id_raddr2 === io.dpath.mem_waddr || id_wen_not0 && id_waddr === io.dpath.mem_waddr) - val fp_data_hazard_mem = mem_reg_fp_wen && + val fp_data_hazard_mem = mem_ctrl.wfd && (io.fpu.dec.ren1 && id_raddr1 === io.dpath.mem_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.mem_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.mem_waddr || io.fpu.dec.wen && id_waddr === io.dpath.mem_waddr) - val id_mem_hazard = data_hazard_mem && (mem_reg_csr != CSR.N || mem_reg_mem_val && mem_mem_cmd_bh || mem_reg_div_mul_val || mem_reg_fp_val || mem_reg_rocc_val) || - fp_data_hazard_mem && mem_reg_fp_val - id_load_use := mem_reg_mem_val && (data_hazard_mem || fp_data_hazard_mem) + val id_mem_hazard = mem_reg_valid && (data_hazard_mem && mem_cannot_bypass || fp_data_hazard_mem) + id_load_use := mem_reg_valid && data_hazard_mem && mem_ctrl.mem // stall for RAW/WAW hazards on load/AMO misses and mul/div in writeback. - val data_hazard_wb = wb_reg_wen && + val data_hazard_wb = wb_ctrl.wxd && (id_renx1_not0 && id_raddr1 === io.dpath.wb_waddr || id_renx2_not0 && id_raddr2 === io.dpath.wb_waddr || id_wen_not0 && id_waddr === io.dpath.wb_waddr) - val fp_data_hazard_wb = wb_reg_fp_wen && + val fp_data_hazard_wb = wb_ctrl.wfd && (io.fpu.dec.ren1 && id_raddr1 === io.dpath.wb_waddr || io.fpu.dec.ren2 && id_raddr2 === io.dpath.wb_waddr || io.fpu.dec.ren3 && id_raddr3 === io.dpath.wb_waddr || io.fpu.dec.wen && id_waddr === io.dpath.wb_waddr) - val id_wb_hazard = data_hazard_wb && wb_set_sboard || - fp_data_hazard_wb && (wb_dcache_miss || wb_reg_fp_val) + val id_wb_hazard = wb_reg_valid && (data_hazard_wb && wb_set_sboard || fp_data_hazard_wb) val id_sboard_hazard = (id_renx1_not0 && sboard.readBypassed(id_raddr1) || @@ -739,52 +644,36 @@ class Control extends Module val ctrl_stalld = id_ex_hazard || id_mem_hazard || id_wb_hazard || id_sboard_hazard || - id_fp_val && id_stall_fpu || - id_mem_val && !io.dmem.req.ready || + id_ctrl.fp && id_stall_fpu || + id_ctrl.mem && !io.dmem.req.ready || id_do_fence - val ctrl_draind = id_interrupt || ex_reg_replay_next + val ctrl_draind = id_interrupt ctrl_killd := !io.imem.resp.valid || take_pc || ctrl_stalld || ctrl_draind io.dpath.killd := take_pc || ctrl_stalld && !ctrl_draind io.imem.resp.ready := !ctrl_stalld || ctrl_draind - io.imem.invalidate := wb_reg_flush_inst + io.imem.invalidate := wb_reg_valid && wb_ctrl.fence_i - io.dpath.mem_load := mem_reg_mem_val && mem_reg_wen - io.dpath.wb_load := wb_reg_mem_val && wb_reg_wen - io.dpath.ren(1) := id_renx2 - io.dpath.ren(0) := id_renx1 - io.dpath.sel_alu2 := id_sel_alu2.toUInt - io.dpath.sel_alu1 := id_sel_alu1.toUInt - io.dpath.sel_imm := id_sel_imm.toUInt - io.dpath.fn_dw := id_fn_dw.toBool - io.dpath.fn_alu := id_fn_alu.toUInt - io.dpath.div_mul_val := ex_reg_div_mul_val - io.dpath.div_mul_kill := mem_reg_div_mul_val && killm_common - io.dpath.ex_fp_val:= ex_reg_fp_val - io.dpath.mem_fp_val:= mem_reg_fp_val - io.dpath.mem_jalr := mem_reg_jalr - io.dpath.mem_branch := mem_reg_branch - io.dpath.ex_wen := ex_reg_wen + io.dpath.ren(1) := id_ctrl.rxs2 + io.dpath.ren(0) := id_ctrl.rxs1 + io.dpath.ex_ctrl := ex_ctrl + io.dpath.mem_ctrl := mem_ctrl io.dpath.ex_valid := ex_reg_valid - io.dpath.mem_wen := mem_reg_wen - io.dpath.ll_ready := !wb_reg_wen - io.dpath.wb_wen := wb_reg_wen && !replay_wb + io.dpath.ll_ready := !(wb_reg_valid && wb_ctrl.wxd) io.dpath.retire := wb_reg_valid && !replay_wb - io.dpath.csr := wb_reg_csr - io.dpath.sret := wb_reg_sret - io.dpath.ex_mem_type := ex_reg_mem_type - io.dpath.ex_rs2_val := ex_reg_mem_val && isWrite(ex_reg_mem_cmd) || ex_reg_rocc_val - io.dpath.ex_rocc_val := ex_reg_rocc_val - io.dpath.mem_rocc_val := mem_reg_rocc_val + io.dpath.wb_wen := io.dpath.retire && wb_ctrl.wxd + io.dpath.csr := Mux(wb_reg_valid, wb_ctrl.csr, CSR.N) + io.dpath.sret := wb_reg_valid && wb_ctrl.sret && !replay_wb + io.dpath.killm := killm_common - io.fpu.valid := !ctrl_killd && id_fp_val + io.fpu.valid := !ctrl_killd && id_ctrl.fp io.fpu.killx := ctrl_killx io.fpu.killm := killm_common - io.dmem.req.valid := ex_reg_mem_val + io.dmem.req.valid := ex_reg_valid && ex_ctrl.mem io.dmem.req.bits.kill := killm_common || mem_xcpt - io.dmem.req.bits.cmd := ex_reg_mem_cmd - io.dmem.req.bits.typ := ex_reg_mem_type + io.dmem.req.bits.cmd := ex_ctrl.mem_cmd + io.dmem.req.bits.typ := ex_ctrl.mem_type io.dmem.req.bits.phys := Bool(false) io.rocc.cmd.valid := wb_rocc_val diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index beff52fb..f60ec7bf 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -22,11 +22,6 @@ class Datapath extends Module // execute definitions val ex_reg_pc = Reg(UInt()) val ex_reg_inst = Reg(Bits()) - val ex_reg_ctrl_fn_dw = Reg(UInt()) - val ex_reg_ctrl_fn_alu = Reg(UInt()) - val ex_reg_sel_alu2 = Reg(UInt()) - val ex_reg_sel_alu1 = Reg(UInt()) - val ex_reg_sel_imm = Reg(UInt()) val ex_reg_kill = Reg(Bool()) val ex_reg_rs_bypass = Vec.fill(2)(Reg(Bool())) val ex_reg_rs_lsb = Vec.fill(2)(Reg(Bits())) @@ -102,11 +97,6 @@ class Datapath extends Module when (!io.ctrl.killd) { ex_reg_pc := id_pc ex_reg_inst := id_inst - ex_reg_ctrl_fn_dw := io.ctrl.fn_dw.toUInt - ex_reg_ctrl_fn_alu := io.ctrl.fn_alu - ex_reg_sel_alu2 := io.ctrl.sel_alu2 - ex_reg_sel_alu1 := io.ctrl.sel_alu1 - ex_reg_sel_imm := io.ctrl.sel_imm ex_reg_rs_bypass := io.ctrl.bypass for (i <- 0 until id_rs.size) { when (io.ctrl.ren(i)) { @@ -129,31 +119,31 @@ class Datapath extends Module val ex_rs = for (i <- 0 until id_rs.size) yield Mux(ex_reg_rs_bypass(i), bypass(ex_reg_rs_lsb(i)), Cat(ex_reg_rs_msb(i), ex_reg_rs_lsb(i))) - val ex_imm = imm(ex_reg_sel_imm, ex_reg_inst) - val ex_op1 = MuxLookup(ex_reg_sel_alu1, SInt(0), Seq( + val ex_imm = imm(io.ctrl.ex_ctrl.sel_imm, ex_reg_inst) + val ex_op1 = MuxLookup(io.ctrl.ex_ctrl.sel_alu1, SInt(0), Seq( A1_RS1 -> ex_rs(0).toSInt, A1_PC -> ex_reg_pc.toSInt)) - val ex_op2 = MuxLookup(ex_reg_sel_alu2, SInt(0), Seq( + val ex_op2 = MuxLookup(io.ctrl.ex_ctrl.sel_alu2, SInt(0), Seq( A2_RS2 -> ex_rs(1).toSInt, A2_IMM -> ex_imm, A2_FOUR -> SInt(4))) val alu = Module(new ALU) - alu.io.dw := ex_reg_ctrl_fn_dw - alu.io.fn := ex_reg_ctrl_fn_alu + alu.io.dw := io.ctrl.ex_ctrl.alu_dw + alu.io.fn := io.ctrl.ex_ctrl.alu_fn alu.io.in2 := ex_op2.toUInt alu.io.in1 := ex_op1 // multiplier and divider val div = Module(new MulDiv(mulUnroll = if(params(FastMulDiv)) 8 else 1, earlyOut = params(FastMulDiv))) - div.io.req.valid := io.ctrl.div_mul_val - div.io.req.bits.dw := ex_reg_ctrl_fn_dw - div.io.req.bits.fn := ex_reg_ctrl_fn_alu + div.io.req.valid := io.ctrl.ex_valid && io.ctrl.ex_ctrl.div + div.io.req.bits.dw := io.ctrl.ex_ctrl.alu_dw + div.io.req.bits.fn := io.ctrl.ex_ctrl.alu_fn div.io.req.bits.in1 := ex_rs(0) div.io.req.bits.in2 := ex_rs(1) div.io.req.bits.tag := io.ctrl.ex_waddr - div.io.kill := io.ctrl.div_mul_kill + div.io.kill := io.ctrl.killm && Reg(next = div.io.req.fire()) io.ctrl.div_mul_rdy := div.io.req.ready io.fpu.fromint_data := ex_rs(0) @@ -171,7 +161,7 @@ class Datapath extends Module // D$ request interface (registered inside D$ module) // other signals (req_val, req_rdy) connect to control module io.dmem.req.bits.addr := Cat(vaSign(ex_rs(0), alu.io.adder_out), alu.io.adder_out(params(VAddrBits)-1,0)).toUInt - io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_fp_val) + io.dmem.req.bits.tag := Cat(io.ctrl.ex_waddr, io.ctrl.ex_ctrl.fp) require(io.dmem.req.bits.tag.getWidth >= 6) require(params(CoreDCacheReqTagBits) >= 6) @@ -196,12 +186,12 @@ class Datapath extends Module mem_reg_pc := ex_reg_pc mem_reg_inst := ex_reg_inst mem_reg_wdata := alu.io.out - } - when (io.ctrl.ex_rs2_val) { - mem_reg_rs2 := ex_rs(1) + when (io.ctrl.ex_ctrl.rxs2 && (io.ctrl.ex_ctrl.mem || io.ctrl.ex_ctrl.rocc)) { + mem_reg_rs2 := ex_rs(1) + } } - io.dmem.req.bits.data := Mux(io.ctrl.mem_fp_val, io.fpu.store_data, mem_reg_rs2) + io.dmem.req.bits.data := Mux(io.ctrl.mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) // writeback arbitration val dmem_resp_xpu = !io.dmem.resp.bits.tag(0).toBool @@ -239,21 +229,21 @@ class Datapath extends Module io.ctrl.mem_br_taken := mem_reg_wdata(0) val mem_br_target = mem_reg_pc + - Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), - Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4))) - val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(params(VAddrBits)-1,0)), mem_br_target) + Mux(io.ctrl.mem_ctrl.branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), + Mux(io.ctrl.mem_ctrl.jal, imm(IMM_UJ, mem_reg_inst), SInt(4))) + val mem_npc = Mux(io.ctrl.mem_ctrl.jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(params(VAddrBits)-1,0)), mem_br_target) io.ctrl.mem_misprediction := mem_npc != ex_reg_pc || !io.ctrl.ex_valid io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1 - val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata) + val mem_int_wdata = Mux(io.ctrl.mem_ctrl.jalr, mem_br_target, mem_reg_wdata) // writeback stage when (!mem_reg_kill) { wb_reg_pc := mem_reg_pc wb_reg_inst := mem_reg_inst - wb_reg_wdata := Mux(io.ctrl.mem_fp_val && io.ctrl.mem_wen, io.fpu.toint_data, mem_int_wdata) - } - when (io.ctrl.mem_rocc_val) { - wb_reg_rs2 := mem_reg_rs2 + wb_reg_wdata := Mux(io.ctrl.mem_ctrl.fp && io.ctrl.mem_ctrl.wxd, io.fpu.toint_data, mem_int_wdata) + when (io.ctrl.mem_ctrl.rocc) { + wb_reg_rs2 := mem_reg_rs2 + } } wb_wdata := Mux(dmem_resp_valid && dmem_resp_xpu, io.dmem.resp.bits.data_subword, Mux(io.ctrl.ll_wen, ll_wdata, diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 7b4cf57e..bb28c7de 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -10,6 +10,9 @@ case object ECCCode extends Field[Option[Code]] abstract trait L1CacheParameters extends CacheParameters with CoreParameters { val co = params(TLCoherence) val code = params(ECCCode).getOrElse(new IdentityCode) + val outerDataBeats = params(TLDataBeats) + val refillCyclesPerBeat = params(TLDataBits)/rowBits + val refillCycles = refillCyclesPerBeat*outerDataBeats } abstract trait FrontendParameters extends L1CacheParameters @@ -106,7 +109,7 @@ class Frontend(btb_updates_out_of_order: Boolean = false) extends FrontendModule icache.io.req.bits.idx := Mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) icache.io.invalidate := io.cpu.invalidate icache.io.req.bits.ppn := tlb.io.resp.ppn - icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss + icache.io.req.bits.kill := io.cpu.req.valid || tlb.io.resp.miss || icmiss || io.cpu.ptw.invalidate icache.io.resp.ready := !stall && !s1_same_block io.cpu.resp.valid := s2_valid && (s2_xcpt_if || icache.io.resp.valid) @@ -187,22 +190,13 @@ class ICache extends FrontendModule val s2_miss = s2_valid && !s2_any_tag_hit rdy := state === s_ready && !s2_miss - var refill_cnt = UInt(0) - var refill_done = state === s_refill - var refill_valid = io.mem.grant.valid - var refill_bits = io.mem.grant.bits - def doRefill(g: Grant): Bool = Bool(true) - if(refillCycles > 1) { - val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, refillCycles, doRefill)) - ser.io.in <> io.mem.grant - refill_cnt = ser.io.cnt - refill_done = ser.io.done - refill_valid = ser.io.out.valid - refill_bits = ser.io.out.bits - ser.io.out.ready := Bool(true) - } else { - io.mem.grant.ready := Bool(true) - } + val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, refillCyclesPerBeat, (g: Grant) => co.messageUpdatesDataArray(g))) + ser.io.in <> io.mem.grant + val (refill_cnt, refill_wrap) = Counter(ser.io.out.fire(), refillCycles) //TODO Zero width wire + val refill_done = state === s_refill && refill_wrap + val refill_valid = ser.io.out.valid + val refill_bits = ser.io.out.bits + ser.io.out.ready := Bool(true) //assert(!c.tlco.isVoluntary(refill_bits.payload) || !refill_valid, "UncachedRequestors shouldn't get voluntary grants.") val repl_way = if (isDM) UInt(0) else LFSR16(s2_miss)(log2Up(nWays)-1,0) @@ -236,7 +230,7 @@ class ICache extends FrontendModule val s2_dout = Vec.fill(nWays){Reg(Bits())} for (i <- 0 until nWays) { - val s1_vb = vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool + val s1_vb = !io.invalidate && vb_array(Cat(UInt(i), s1_pgoff(untagBits-1,blockOffBits))).toBool val s2_vb = Reg(Bool()) val s2_tag_disparity = Reg(Bool()) val s2_tag_match = Reg(Bool()) @@ -257,8 +251,8 @@ class ICache extends FrontendModule val s1_raddr = Reg(UInt()) when (refill_valid && repl_way === UInt(i)) { val e_d = code.encode(refill_bits.payload.data) - if(refillCycles > 1) data_array(Cat(s2_idx,refill_cnt)) := e_d - else data_array(s2_idx) := e_d + if(refillCycles > 1) data_array(Cat(s2_idx, refill_cnt)) := e_d + else data_array(s2_idx) := e_d } // /*.else*/when (s0_valid) { // uncomment ".else" to infer 6T SRAM .elsewhen (s0_valid) { @@ -272,14 +266,14 @@ class ICache extends FrontendModule io.resp.bits.datablock := Mux1H(s2_tag_hit, s2_dout) val ack_q = Module(new Queue(new LogicalNetworkIO(new Finish), 1)) - ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload.g_type) - ack_q.io.enq.bits.payload.master_xact_id := refill_bits.payload.master_xact_id + ack_q.io.enq.valid := refill_done && co.requiresAckForGrant(refill_bits.payload) + ack_q.io.enq.bits.payload.manager_xact_id := refill_bits.payload.manager_xact_id ack_q.io.enq.bits.header.dst := refill_bits.header.src // output signals io.resp.valid := s2_hit io.mem.acquire.valid := (state === s_request) && ack_q.io.enq.ready - io.mem.acquire.bits.payload := Acquire(co.getUncachedReadAcquireType, s2_addr >> UInt(blockOffBits), UInt(0)) + io.mem.acquire.bits.payload := UncachedRead(s2_addr >> UInt(blockOffBits)) io.mem.finish <> ack_q.io.deq // control state machine diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 3d9bc150..7fa3044c 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -13,13 +13,15 @@ case object LRSCCycles extends Field[Int] case object NDTLBEntries extends Field[Int] abstract trait L1HellaCacheParameters extends L1CacheParameters { - val indexmsb = untagBits-1 - val indexlsb = blockOffBits - val offsetmsb = indexlsb-1 + val idxMSB = untagBits-1 + val idxLSB = blockOffBits + val offsetmsb = idxLSB-1 val offsetlsb = wordOffBits val doNarrowRead = coreDataBits * nWays % rowBits == 0 val encDataBits = code.width(coreDataBits) val encRowBits = encDataBits*rowWords + val sdqDepth = params(StoreDataQueueDepth) + val nMSHRs = params(NMSHRs) } abstract class L1HellaCacheBundle extends Bundle with L1HellaCacheParameters @@ -57,22 +59,28 @@ class LoadGen(typ: Bits, addr: Bits, dat: Bits, zero: Bool) val byte = Cat(Mux(zero || t.byte, Fill(56, sign && byteShift(7)), half(63,8)), byteShift) } -class HellaCacheReq extends CoreBundle { +trait HasCoreData extends CoreBundle { + val data = Bits(width = coreDataBits) +} + +class HellaCacheReqInternal extends CoreBundle { val kill = Bool() val typ = Bits(width = MT_SZ) val phys = Bool() val addr = UInt(width = coreMaxAddrBits) - val data = Bits(width = coreDataBits) val tag = Bits(width = coreDCacheReqTagBits) val cmd = Bits(width = M_SZ) } -class HellaCacheResp extends CoreBundle { +class HellaCacheReq extends HellaCacheReqInternal + with HasCoreData + +class HellaCacheResp extends CoreBundle + with HasCoreData { val nack = Bool() // comes 2 cycles after req.fire val replay = Bool() val typ = Bits(width = 3) val has_data = Bool() - val data = Bits(width = coreDataBits) val data_subword = Bits(width = coreDataBits) val tag = Bits(width = coreDCacheReqTagBits) val cmd = Bits(width = 4) @@ -100,15 +108,20 @@ class HellaCacheIO extends CoreBundle { val ordered = Bool(INPUT) } -class MSHRReq extends HellaCacheReq with L1HellaCacheParameters { +trait HasSDQId extends CoreBundle with L1HellaCacheParameters { + val sdq_id = UInt(width = log2Up(sdqDepth)) +} + +trait HasMissInfo extends CoreBundle with L1HellaCacheParameters { val tag_match = Bool() val old_meta = new L1Metadata val way_en = Bits(width = nWays) } -class Replay extends HellaCacheReq with L1HellaCacheParameters { - val sdq_id = UInt(width = log2Up(params(StoreDataQueueDepth))) -} +class Replay extends HellaCacheReqInternal with HasCoreData +class ReplayInternal extends HellaCacheReqInternal with HasSDQId +class MSHRReq extends Replay with HasMissInfo +class MSHRReqInternal extends ReplayInternal with HasMissInfo class DataReadReq extends L1HellaCacheBundle { val way_en = Bits(width = nWays) @@ -146,7 +159,6 @@ class WritebackReq extends L1HellaCacheBundle { val idx = Bits(width = idxBits) val way_en = Bits(width = nWays) val client_xact_id = Bits(width = params(TLClientXactIdBits)) - val master_xact_id = Bits(width = params(TLMasterXactIdBits)) val r_type = UInt(width = co.releaseTypeWidth) } @@ -156,8 +168,7 @@ class MSHR(id: Int) extends L1HellaCacheModule { val req_pri_rdy = Bool(OUTPUT) val req_sec_val = Bool(INPUT) val req_sec_rdy = Bool(OUTPUT) - val req_bits = new MSHRReq().asInput - val req_sdq_id = UInt(INPUT, log2Up(params(StoreDataQueueDepth))) + val req_bits = new MSHRReqInternal().asInput val idx_match = Bool(OUTPUT) val tag = Bits(OUTPUT, tagBits) @@ -166,7 +177,7 @@ class MSHR(id: Int) extends L1HellaCacheModule { val mem_resp = new DataWriteReq().asOutput val meta_read = Decoupled(new L1MetaReadReq) val meta_write = Decoupled(new L1MetaWriteReq) - val replay = Decoupled(new Replay) + val replay = Decoupled(new ReplayInternal) val mem_grant = Valid(new LogicalNetworkIO(new Grant)).flip val mem_finish = Decoupled(new LogicalNetworkIO(new Finish)) val wb_req = Decoupled(new WritebackReq) @@ -178,28 +189,25 @@ class MSHR(id: Int) extends L1HellaCacheModule { val acquire_type = Reg(UInt()) val release_type = Reg(UInt()) - val line_state = Reg(new ClientMetadata()(co)) - val refill_count = Reg(UInt(width = log2Up(refillCycles))) // TODO: zero-width wire - val req = Reg(new MSHRReq()) + val line_state = Reg(new ClientMetadata) + val req = Reg(new MSHRReqInternal()) val req_cmd = io.req_bits.cmd val req_idx = req.addr(untagBits-1,blockOffBits) val idx_match = req_idx === io.req_bits.addr(untagBits-1,blockOffBits) val sec_rdy = idx_match && (state === s_wb_req || state === s_wb_resp || state === s_meta_clear || (state === s_refill_req || state === s_refill_resp) && !co.needsTransactionOnSecondaryMiss(req_cmd, io.mem_req.bits)) - require(isPow2(refillCycles)) val reply = io.mem_grant.valid && io.mem_grant.bits.payload.client_xact_id === UInt(id) - val refill_done = reply && (if(refillCycles > 1) refill_count.andR else Bool(true)) + val (refill_cnt, refill_done) = Counter(reply && co.messageUpdatesDataArray(io.mem_grant.bits.payload), refillCycles) // TODO: Zero width? val wb_done = reply && (state === s_wb_resp) val meta_on_flush = co.clientMetadataOnFlush val meta_on_grant = co.clientMetadataOnGrant(io.mem_grant.bits.payload, io.mem_req.bits) val meta_on_hit = co.clientMetadataOnHit(req_cmd, io.req_bits.old_meta.coh) - val rpq = Module(new Queue(new Replay, params(ReplayQueueDepth))) + val rpq = Module(new Queue(new ReplayInternal, params(ReplayQueueDepth))) rpq.io.enq.valid := (io.req_pri_val && io.req_pri_rdy || io.req_sec_val && sec_rdy) && !isPrefetch(req_cmd) rpq.io.enq.bits := io.req_bits - rpq.io.enq.bits.sdq_id := io.req_sdq_id rpq.io.deq.ready := io.replay.ready && state === s_drain_rpq || state === s_invalid when (state === s_drain_rpq && !rpq.io.deq.valid) { @@ -213,11 +221,8 @@ class MSHR(id: Int) extends L1HellaCacheModule { state := s_meta_write_resp } when (state === s_refill_resp) { + when (reply) { line_state := meta_on_grant } when (refill_done) { state := s_meta_write_req } - when (reply) { - if(refillCycles > 1) refill_count := refill_count + UInt(1) - line_state := meta_on_grant - } } when (io.mem_req.fire()) { // s_refill_req state := s_refill_resp @@ -231,13 +236,12 @@ class MSHR(id: Int) extends L1HellaCacheModule { when (io.wb_req.fire()) { // s_wb_req state := s_wb_resp } - when (io.req_sec_val && io.req_sec_rdy) { // s_wb_req, s_wb_resp, s_refill_req acquire_type := co.getAcquireTypeOnSecondaryMiss(req_cmd, meta_on_flush, io.mem_req.bits) } when (io.req_pri_val && io.req_pri_rdy) { line_state := meta_on_flush - refill_count := UInt(0) + refill_cnt := UInt(0) acquire_type := co.getAcquireTypeOnPrimaryMiss(req_cmd, meta_on_flush) release_type := co.getReleaseTypeOnVoluntaryWriteback() //TODO downgrades etc req := io.req_bits @@ -255,8 +259,8 @@ class MSHR(id: Int) extends L1HellaCacheModule { } val ackq = Module(new Queue(new LogicalNetworkIO(new Finish), 1)) - ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload.g_type) - ackq.io.enq.bits.payload.master_xact_id := io.mem_grant.bits.payload.master_xact_id + ackq.io.enq.valid := (wb_done || refill_done) && co.requiresAckForGrant(io.mem_grant.bits.payload) + ackq.io.enq.bits.payload.manager_xact_id := io.mem_grant.bits.payload.manager_xact_id ackq.io.enq.bits.header.dst := io.mem_grant.bits.header.src val can_finish = state === s_invalid || state === s_refill_req || state === s_refill_resp io.mem_finish.valid := ackq.io.deq.valid && can_finish @@ -265,7 +269,7 @@ class MSHR(id: Int) extends L1HellaCacheModule { io.idx_match := (state != s_invalid) && idx_match io.mem_resp := req - io.mem_resp.addr := (if(refillCycles > 1) Cat(req_idx, refill_count) else req_idx) << rowOffBits + io.mem_resp.addr := (if(refillCycles > 1) Cat(req_idx, refill_cnt) else req_idx) << rowOffBits io.tag := req.addr >> untagBits io.req_pri_rdy := state === s_invalid io.req_sec_rdy := sec_rdy && rpq.io.enq.ready @@ -286,13 +290,10 @@ class MSHR(id: Int) extends L1HellaCacheModule { io.wb_req.bits.idx := req_idx io.wb_req.bits.way_en := req.way_en io.wb_req.bits.client_xact_id := Bits(id) - io.wb_req.bits.master_xact_id := Bits(0) // DNC io.wb_req.bits.r_type := co.getReleaseTypeOnVoluntaryWriteback() io.mem_req.valid := state === s_refill_req && ackq.io.enq.ready - io.mem_req.bits.a_type := acquire_type - io.mem_req.bits.addr := Cat(io.tag, req_idx).toUInt - io.mem_req.bits.client_xact_id := Bits(id) + io.mem_req.bits := Acquire(acquire_type, Cat(io.tag, req_idx).toUInt, Bits(id)) io.mem_finish <> ackq.io.deq io.meta_read.valid := state === s_drain_rpq @@ -328,26 +329,26 @@ class MSHRFile extends L1HellaCacheModule { val fence_rdy = Bool(OUTPUT) } - val sdq_val = Reg(init=Bits(0, params(StoreDataQueueDepth))) - val sdq_alloc_id = PriorityEncoder(~sdq_val(params(StoreDataQueueDepth)-1,0)) + val sdq_val = Reg(init=Bits(0, sdqDepth)) + val sdq_alloc_id = PriorityEncoder(~sdq_val(sdqDepth-1,0)) val sdq_rdy = !sdq_val.andR val sdq_enq = io.req.valid && io.req.ready && isWrite(io.req.bits.cmd) - val sdq = Mem(io.req.bits.data, params(StoreDataQueueDepth)) + val sdq = Mem(io.req.bits.data, sdqDepth) when (sdq_enq) { sdq(sdq_alloc_id) := io.req.bits.data } - val idxMatch = Vec.fill(params(NMSHRs)){Bool()} - val tagList = Vec.fill(params(NMSHRs)){Bits()} + val idxMatch = Vec.fill(nMSHRs){Bool()} + val tagList = Vec.fill(nMSHRs){Bits()} val tag_match = Mux1H(idxMatch, tagList) === io.req.bits.addr >> untagBits - val wbTagList = Vec.fill(params(NMSHRs)){Bits()} - val memRespMux = Vec.fill(params(NMSHRs)){new DataWriteReq} - val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, params(NMSHRs))) - val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, params(NMSHRs))) - val mem_req_arb = Module(new Arbiter(new Acquire, params(NMSHRs))) - val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), params(NMSHRs))) - val wb_req_arb = Module(new Arbiter(new WritebackReq, params(NMSHRs))) - val replay_arb = Module(new Arbiter(new Replay, params(NMSHRs))) - val alloc_arb = Module(new Arbiter(Bool(), params(NMSHRs))) + val wbTagList = Vec.fill(nMSHRs){Bits()} + val memRespMux = Vec.fill(nMSHRs){new DataWriteReq} + val meta_read_arb = Module(new Arbiter(new L1MetaReadReq, nMSHRs)) + val meta_write_arb = Module(new Arbiter(new L1MetaWriteReq, nMSHRs)) + val mem_req_arb = Module(new LockingArbiter(new Acquire, nMSHRs, outerDataBeats, co.messageHasData _)) + val mem_finish_arb = Module(new Arbiter(new LogicalNetworkIO(new Finish), nMSHRs)) + val wb_req_arb = Module(new Arbiter(new WritebackReq, nMSHRs)) + val replay_arb = Module(new Arbiter(new ReplayInternal, nMSHRs)) + val alloc_arb = Module(new Arbiter(Bool(), nMSHRs)) var idx_match = Bool(false) var pri_rdy = Bool(false) @@ -356,7 +357,7 @@ class MSHRFile extends L1HellaCacheModule { io.fence_rdy := true io.probe_rdy := true - for (i <- 0 until params(NMSHRs)) { + for (i <- 0 until nMSHRs) { val mshr = Module(new MSHR(i)) idxMatch(i) := mshr.io.idx_match @@ -368,7 +369,7 @@ class MSHRFile extends L1HellaCacheModule { mshr.io.req_sec_val := io.req.valid && sdq_rdy && tag_match mshr.io.req_bits := io.req.bits - mshr.io.req_sdq_id := sdq_alloc_id + mshr.io.req_bits.sdq_id := sdq_alloc_id mshr.io.meta_read <> meta_read_arb.io.in(i) mshr.io.meta_write <> meta_write_arb.io.in(i) @@ -405,8 +406,8 @@ class MSHRFile extends L1HellaCacheModule { io.replay <> replay_arb.io.out when (io.replay.valid || sdq_enq) { - sdq_val := sdq_val & ~(UIntToOH(io.replay.bits.sdq_id) & Fill(params(StoreDataQueueDepth), free_sdq)) | - PriorityEncoderOH(~sdq_val(params(StoreDataQueueDepth)-1,0)) & Fill(params(StoreDataQueueDepth), sdq_enq) + sdq_val := sdq_val & ~(UIntToOH(replay_arb.io.out.bits.sdq_id) & Fill(sdqDepth, free_sdq)) | + PriorityEncoderOH(~sdq_val(sdqDepth-1,0)) & Fill(sdqDepth, sdq_enq) } } @@ -422,7 +423,9 @@ class WritebackUnit extends L1HellaCacheModule { val active = Reg(init=Bool(false)) val r1_data_req_fired = Reg(init=Bool(false)) val r2_data_req_fired = Reg(init=Bool(false)) - val cnt = Reg(init = UInt(0, width = log2Up(refillCycles+1))) + val cnt = Reg(init = UInt(0, width = log2Up(refillCycles+1))) //TODO Zero width + val buf_v = (if(refillCyclesPerBeat > 1) Reg(init=Bits(0, width = refillCyclesPerBeat-1)) else Bits(1)) + val beat_done = buf_v.andR val req = Reg(new WritebackReq) io.release.valid := false @@ -433,27 +436,22 @@ class WritebackUnit extends L1HellaCacheModule { r1_data_req_fired := true cnt := cnt + 1 } - if(refillCycles > 1) { // Coalescing buffer inserted - when (!r1_data_req_fired && !r2_data_req_fired && cnt === refillCycles) { - io.release.valid := true - active := !io.release.ready - } - } else { // No buffer, data released a cycle earlier - when (r2_data_req_fired) { - io.release.valid := true - when(!io.release.ready) { - r1_data_req_fired := false - r2_data_req_fired := false - cnt := UInt(0) - } .otherwise { - active := false - } + when (r2_data_req_fired) { + io.release.valid := beat_done + when(!io.release.ready) { + r1_data_req_fired := false + r2_data_req_fired := false + cnt := cnt - Mux[UInt](Bool(refillCycles > 1) && r1_data_req_fired, 2, 1) + } .elsewhen(beat_done) { if(refillCyclesPerBeat > 1) buf_v := 0 } + when(!r1_data_req_fired) { + active := cnt < UInt(refillCycles) } } } when (io.req.fire()) { active := true cnt := 0 + if(refillCyclesPerBeat > 1) buf_v := 0 req := io.req.bits } @@ -467,26 +465,23 @@ class WritebackUnit extends L1HellaCacheModule { io.data_req.valid := fire io.data_req.bits.way_en := req.way_en - if(refillCycles > 1) { - io.data_req.bits.addr := Cat(req.idx, cnt(log2Up(refillCycles)-1,0)) << rowOffBits - } else { - io.data_req.bits.addr := req.idx << rowOffBits - } + io.data_req.bits.addr := (if(refillCycles > 1) Cat(req.idx, cnt(log2Up(refillCycles)-1,0)) + else req.idx) << rowOffBits io.release.bits.r_type := req.r_type io.release.bits.addr := Cat(req.tag, req.idx).toUInt io.release.bits.client_xact_id := req.client_xact_id - io.release.bits.master_xact_id := req.master_xact_id - if(refillCycles > 1) { - val data_buf = Reg(Bits()) - when(active && r2_data_req_fired) { - data_buf := Cat(io.data_resp, data_buf(refillCycles*encRowBits-1, encRowBits)) - } - io.release.bits.data := data_buf - } else { - io.release.bits.data := io.data_resp - } - + io.release.bits.data := + (if(refillCyclesPerBeat > 1) { + val data_buf = Reg(Bits()) + when(active && r2_data_req_fired && !beat_done) { + data_buf := Cat(io.data_resp, data_buf((refillCyclesPerBeat-1)*encRowBits-1, encRowBits)) + buf_v := (if(refillCyclesPerBeat > 2) + Cat(UInt(1), buf_v(refillCyclesPerBeat-2,1)) + else UInt(1)) + } + Cat(io.data_resp, data_buf) + } else { io.data_resp }) } class ProbeUnit extends L1HellaCacheModule { @@ -498,7 +493,7 @@ class ProbeUnit extends L1HellaCacheModule { val wb_req = Decoupled(new WritebackReq) val way_en = Bits(INPUT, nWays) val mshr_rdy = Bool(INPUT) - val line_state = new ClientMetadata()(co).asInput + val line_state = new ClientMetadata().asInput } val s_reset :: s_invalid :: s_meta_read :: s_meta_resp :: s_mshr_req :: s_release :: s_writeback_req :: s_writeback_resp :: s_meta_write :: Nil = Enum(UInt(), 9) @@ -544,8 +539,12 @@ class ProbeUnit extends L1HellaCacheModule { } io.req.ready := state === s_invalid - io.rep.valid := state === s_release && !(hit && co.needsWriteback(line_state)) - io.rep.bits := Release(co.getReleaseTypeOnProbe(req, Mux(hit, line_state, co.clientMetadataOnFlush)), req.addr, req.client_xact_id, req.master_xact_id) + io.rep.valid := state === s_release && + !(hit && co.needsWriteback(line_state)) // Otherwise WBU will issue release + io.rep.bits := Release(co.getReleaseTypeOnProbe(req, + Mux(hit, line_state, co.clientMetadataOnFlush)), + req.addr, + req.client_xact_id) io.meta_read.valid := state === s_meta_read io.meta_read.bits.idx := req.addr @@ -563,7 +562,6 @@ class ProbeUnit extends L1HellaCacheModule { io.wb_req.bits.tag := req.addr >> UInt(idxBits) io.wb_req.bits.r_type := co.getReleaseTypeOnProbe(req, Mux(hit, line_state, co.clientMetadataOnFlush)) io.wb_req.bits.client_xact_id := req.client_xact_id - io.wb_req.bits.master_xact_id := req.master_xact_id } class DataArray extends L1HellaCacheModule { @@ -747,7 +745,7 @@ class HellaCache extends L1HellaCacheModule { io.cpu.xcpt.pf.st := s1_write && dtlb.io.resp.xcpt_st // tags - def onReset = L1Metadata(UInt(0), ClientMetadata(UInt(0))(co)) + def onReset = L1Metadata(UInt(0), ClientMetadata(UInt(0))) val meta = Module(new MetadataArray(onReset _)) val metaReadArb = Module(new Arbiter(new MetaReadReq, 5)) val metaWriteArb = Module(new Arbiter(new L1MetaWriteReq, 2)) @@ -872,8 +870,8 @@ class HellaCache extends L1HellaCacheModule { metaReadArb.io.in(1) <> mshrs.io.meta_read metaWriteArb.io.in(0) <> mshrs.io.meta_write - // probes - val releaseArb = Module(new Arbiter(new Release, 2)) + // probes and releases + val releaseArb = Module(new LockingArbiter(new Release, 2, outerDataBeats, co.messageHasData _)) DecoupledLogicalNetworkIOWrapper(releaseArb.io.out) <> io.mem.release val probe = DecoupledLogicalNetworkIOUnwrapper(io.mem.probe) @@ -889,11 +887,9 @@ class HellaCache extends L1HellaCacheModule { // refills def doRefill(g: Grant): Bool = co.messageUpdatesDataArray(g) - val refill = if(refillCycles > 1) { - val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, refillCycles, doRefill)) - ser.io.in <> io.mem.grant - ser.io.out - } else io.mem.grant + val ser = Module(new FlowThroughSerializer(io.mem.grant.bits, refillCyclesPerBeat, doRefill)) + ser.io.in <> io.mem.grant + val refill = ser.io.out mshrs.io.mem_grant.valid := refill.fire() mshrs.io.mem_grant.bits := refill.bits refill.ready := writeArb.io.in(1).ready || !doRefill(refill.bits.payload) @@ -943,7 +939,7 @@ class HellaCache extends L1HellaCacheModule { // nack it like it's hot val s1_nack = dtlb.io.req.valid && dtlb.io.resp.miss || - s1_req.addr(indexmsb,indexlsb) === prober.io.meta_write.bits.idx && !prober.io.req.ready + s1_req.addr(idxMSB,idxLSB) === prober.io.meta_write.bits.idx && !prober.io.req.ready val s2_nack_hit = RegEnable(s1_nack, s1_valid || s1_replay) when (s2_nack_hit) { mshrs.io.req.valid := Bool(false) } val s2_nack_victim = s2_hit && mshrs.io.secondary_miss diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index d3099043..68cef693 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -43,6 +43,7 @@ class RoCCInterface extends Bundle // These should be handled differently, eventually val imem = new UncachedTileLinkIO + val dmem = new TileLinkIO val iptw = new TLBPTWIO val dptw = new TLBPTWIO val pptw = new TLBPTWIO @@ -124,6 +125,11 @@ class AccumulatorExample extends RoCC io.imem.acquire.valid := false io.imem.grant.ready := false io.imem.finish.valid := false + io.dmem.acquire.valid := false + io.dmem.release.valid := false + io.dmem.finish.valid := false + io.dmem.probe.ready := false + io.dmem.grant.ready := false io.iptw.req.valid := false io.dptw.req.valid := false io.pptw.req.valid := false diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index 04c7753d..4ad0897d 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -38,10 +38,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { core.io.imem <> icache.io.cpu core.io.ptw <> ptw.io.dpath - val memArb = Module(new UncachedTileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts))) - val dcPortId = 0 - memArb.io.in(dcPortId) <> dcache.io.mem - memArb.io.in(1) <> icache.io.mem + val memArb = Module(new TileLinkIOArbiterThatAppendsArbiterId(params(NTilePorts))) + io.tilelink <> memArb.io.out + memArb.io.in(0) <> dcache.io.mem + memArb.io.in(1) <> TileLinkIOWrapper(icache.io.mem) //If so specified, build an RoCC module and wire it in params(BuildRoCC) @@ -51,21 +51,10 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { core.io.rocc <> rocc.io dcIF.io.requestor <> rocc.io.mem dcArb.io.requestor(2) <> dcIF.io.cache - memArb.io.in(2) <> rocc.io.imem + memArb.io.in(2) <> TileLinkIOWrapper(rocc.io.imem) + memArb.io.in(3) <> rocc.io.dmem ptw.io.requestor(2) <> rocc.io.iptw ptw.io.requestor(3) <> rocc.io.dptw ptw.io.requestor(4) <> rocc.io.pptw } - - io.tilelink.acquire <> memArb.io.out.acquire - io.tilelink.grant <> memArb.io.out.grant - io.tilelink.finish <> memArb.io.out.finish - // Probes and releases routed directly to coherent dcache - io.tilelink.probe <> dcache.io.mem.probe - // Mimic client id extension done by UncachedTileLinkIOArbiter for Acquires from either client) - io.tilelink.release.valid := dcache.io.mem.release.valid - dcache.io.mem.release.ready := io.tilelink.release.ready - io.tilelink.release.bits := dcache.io.mem.release.bits - io.tilelink.release.bits.payload.client_xact_id := Cat(dcache.io.mem.release.bits.payload.client_xact_id, UInt(dcPortId, log2Up(params(NTilePorts)))) - } diff --git a/rocket/src/main/scala/util.scala b/rocket/src/main/scala/util.scala index 485dc57f..464fdbb2 100644 --- a/rocket/src/main/scala/util.scala +++ b/rocket/src/main/scala/util.scala @@ -158,50 +158,3 @@ object Random private def partition(value: UInt, slices: Int) = Vec.tabulate(slices)(i => value < round((i << value.getWidth).toDouble / slices)) } - -class FlowThroughSerializer[T <: HasTileLinkData](gen: LogicalNetworkIO[T], n: Int, doSer: T => Bool) extends Module { - val io = new Bundle { - val in = Decoupled(gen.clone).flip - val out = Decoupled(gen.clone) - val cnt = UInt(OUTPUT, log2Up(n)) - val done = Bool(OUTPUT) - } - require(io.in.bits.payload.data.getWidth % n == 0) - val narrowWidth = io.in.bits.payload.data.getWidth / n - val cnt = Reg(init=UInt(0, width = log2Up(n))) - val wrap = cnt === UInt(n-1) - val rbits = Reg(init=io.in.bits) - val active = Reg(init=Bool(false)) - - val shifter = Vec.fill(n){Bits(width = narrowWidth)} - (0 until n).foreach { - i => shifter(i) := rbits.payload.data((i+1)*narrowWidth-1,i*narrowWidth) - } - - io.done := Bool(false) - io.cnt := cnt - io.in.ready := !active - io.out.valid := active || io.in.valid - io.out.bits := io.in.bits - when(!active && io.in.valid) { - when(doSer(io.in.bits.payload)) { - cnt := Mux(io.out.ready, UInt(1), UInt(0)) - rbits := io.in.bits - active := Bool(true) - } - io.done := !doSer(io.in.bits.payload) - } - when(active) { - io.out.bits := rbits - io.out.bits.payload.data := shifter(cnt) - when(io.out.ready) { - cnt := cnt + UInt(1) - when(wrap) { - cnt := UInt(0) - io.done := Bool(true) - active := Bool(false) - } - } - } -} -