tile: put a BasicBusBlocker inside RocketTile (#1115)

...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.

src/main/scala/tile/BaseTile.scala

@@ -23,6 +23,7 @@ trait TileParams {
   val btb: Option[BTBParams]
   val trace: Boolean
   val hartid: Int
+  val blockerCtrlAddr: Option[BigInt]
 }
 
 trait HasTileParameters {
@@ -85,7 +86,6 @@ trait HasTileLinkMasterPort {
   val module: HasTileLinkMasterPortModule
   val masterNode = TLIdentityNode()
   val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to
-  masterNode := tileBus.node
 }
 
 trait HasTileLinkMasterPortBundle {

src/main/scala/tile/RocketTile.scala

@@ -23,6 +23,7 @@ case class RocketTileParams(
     hcfOnUncorrectable: Boolean = false,
     name: Option[String] = Some("tile"),
     hartid: Int = 0,
+    blockerCtrlAddr: Option[BigInt] = None,
     boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs?
     ) extends TileParams {
   require(icache.isDefined)