From b625e683605ed0fb3abb1577957144b06b82c63c Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Fri, 17 Nov 2017 17:26:48 -0800 Subject: [PATCH] tile: put a BasicBusBlocker inside RocketTile (#1115) ...instead of on the master side of the system bus. People inheriting from HasTileMasterPort might need to add `masterNode := tileBus.node` to their Tile child class. --- src/main/scala/coreplex/RocketCoreplex.scala | 13 +++---------- src/main/scala/devices/tilelink/BusBlocker.scala | 6 +++--- src/main/scala/groundtest/TraceGen.scala | 1 + src/main/scala/rocket/ScratchpadSlavePort.scala | 11 ++++++++++- src/main/scala/tile/BaseTile.scala | 2 +- src/main/scala/tile/RocketTile.scala | 1 + 6 files changed, 19 insertions(+), 15 deletions(-) diff --git a/src/main/scala/coreplex/RocketCoreplex.scala b/src/main/scala/coreplex/RocketCoreplex.scala index 7cf9b155..06e971a5 100644 --- a/src/main/scala/coreplex/RocketCoreplex.scala +++ b/src/main/scala/coreplex/RocketCoreplex.scala @@ -16,23 +16,16 @@ import freechips.rocketchip.util._ // TODO: how specific are these to RocketTiles? case class TileMasterPortParams( addBuffers: Int = 0, - blockerCtrlAddr: Option[BigInt] = None, cork: Option[Boolean] = None) { def adapt(coreplex: HasPeripheryBus) (masterNode: TLOutwardNode) (implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = { val tile_master_cork = cork.map(u => (LazyModule(new TLCacheCork(unsafe = u)))) - val tile_master_blocker = - blockerCtrlAddr - .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes, deadlock = true)) - .map(bp => LazyModule(new BasicBusBlocker(bp))) val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable)) - tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves } - (Seq(tile_master_fixer.node) ++ TLBuffer.chain(addBuffers) - ++ tile_master_blocker.map(_.node) ++ tile_master_cork.map(_.node)) - .foldRight(masterNode)(_ :=* _) + (Seq(tile_master_fixer.node) ++ TLBuffer.chain(addBuffers) ++ tile_master_cork.map(_.node)) + .foldRight(masterNode)(_ :=* _) } } @@ -45,7 +38,7 @@ case class TileSlavePortParams( (implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = { val tile_slave_blocker = blockerCtrlAddr - .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes)) + .map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes)) .map(bp => LazyModule(new BasicBusBlocker(bp))) tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves } diff --git a/src/main/scala/devices/tilelink/BusBlocker.scala b/src/main/scala/devices/tilelink/BusBlocker.scala index 3ff76d19..63e3ccb7 100644 --- a/src/main/scala/devices/tilelink/BusBlocker.scala +++ b/src/main/scala/devices/tilelink/BusBlocker.scala @@ -62,8 +62,8 @@ object DevicePMP case class BusBlockerParams( controlAddress: BigInt, controlBeatBytes: Int, - deviceBeatBytes: Int, - pmpRegisters: Int) + deviceBeatBytes: Int = 1, // TODO: This is ignored by the BusBypassBar + pmpRegisters: Int = 1) { val page = 4096 val pageBits = log2Ceil(page) @@ -115,7 +115,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus case class BasicBusBlockerParams( controlAddress: BigInt, controlBeatBytes: Int, - deviceBeatBytes: Int, + deviceBeatBytes: Int = 1, // TODO: this is ignored by the BusBypassBar deadlock: Boolean = false) class BasicBusBlocker(params: BasicBusBlockerParams)(implicit p: Parameters) diff --git a/src/main/scala/groundtest/TraceGen.scala b/src/main/scala/groundtest/TraceGen.scala index 5d10d30e..13ddd369 100644 --- a/src/main/scala/groundtest/TraceGen.scala +++ b/src/main/scala/groundtest/TraceGen.scala @@ -67,6 +67,7 @@ case class TraceGenParams( def build(i: Int, p: Parameters): GroundTestTile = new TraceGenTile(i, this)(p) val hartid = 0 val trace = false + val blockerCtrlAddr = None } trait HasTraceGenParams { diff --git a/src/main/scala/rocket/ScratchpadSlavePort.scala b/src/main/scala/rocket/ScratchpadSlavePort.scala index 3a94e0d7..5a471096 100644 --- a/src/main/scala/rocket/ScratchpadSlavePort.scala +++ b/src/main/scala/rocket/ScratchpadSlavePort.scala @@ -7,6 +7,7 @@ import Chisel.ImplicitConversions._ import freechips.rocketchip.config.Parameters import freechips.rocketchip.coreplex.CacheBlockBytes +import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tile._ import freechips.rocketchip.tilelink._ @@ -110,13 +111,21 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend { beu } + val tile_master_blocker = + tileParams.blockerCtrlAddr + .map(BasicBusBlockerParams(_, xBytes, deadlock = true)) + .map(bp => LazyModule(new BasicBusBlocker(bp))) + + masterNode := tile_master_blocker.map { _.node := tileBus.node } getOrElse { tileBus.node } + // connect any combination of ITIM, DTIM, and BusErrorUnit val slaveNode = TLIdentityNode() DisableMonitors { implicit p => val xbarPorts = scratch.map(lm => (lm.node, xBytes)) ++ busErrorUnit.map(lm => (lm.node, xBytes)) ++ - tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes))) + tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes))) ++ + tile_master_blocker.map( lm => (lm.controlNode, xBytes)) if (xbarPorts.nonEmpty) { val xbar = LazyModule(new TLXbar) diff --git a/src/main/scala/tile/BaseTile.scala b/src/main/scala/tile/BaseTile.scala index d6c907fc..dfa84a58 100644 --- a/src/main/scala/tile/BaseTile.scala +++ b/src/main/scala/tile/BaseTile.scala @@ -23,6 +23,7 @@ trait TileParams { val btb: Option[BTBParams] val trace: Boolean val hartid: Int + val blockerCtrlAddr: Option[BigInt] } trait HasTileParameters { @@ -85,7 +86,6 @@ trait HasTileLinkMasterPort { val module: HasTileLinkMasterPortModule val masterNode = TLIdentityNode() val tileBus = LazyModule(new TLXbar) // TileBus xbar for cache backends to connect to - masterNode := tileBus.node } trait HasTileLinkMasterPortBundle { diff --git a/src/main/scala/tile/RocketTile.scala b/src/main/scala/tile/RocketTile.scala index cd8a9cea..ebfcde9d 100644 --- a/src/main/scala/tile/RocketTile.scala +++ b/src/main/scala/tile/RocketTile.scala @@ -23,6 +23,7 @@ case class RocketTileParams( hcfOnUncorrectable: Boolean = false, name: Option[String] = Some("tile"), hartid: Int = 0, + blockerCtrlAddr: Option[BigInt] = None, boundaryBuffers: Boolean = false // if synthesized with hierarchical PnR, cut feed-throughs? ) extends TileParams { require(icache.isDefined)