riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: put a BasicBusBlocker inside RocketTile (#1115)

Browse Source 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
This commit is contained in:
Henry Cook
2017-11-17 17:26:48 -08:00
committed by GitHub
parent e7704f46c8
commit b625e68360
6 changed files with 19 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
src/main/scala/rocket/ScratchpadSlavePort.scala
View File

@ -7,6 +7,7 @@ import Chisel.ImplicitConversions._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.coreplex.CacheBlockBytes
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink._
@ -110,13 +111,21 @@ trait CanHaveScratchpad extends HasHellaCache with HasICacheFrontend {
beu
}
val tile_master_blocker =
tileParams.blockerCtrlAddr
.map(BasicBusBlockerParams(_, xBytes, deadlock = true))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
masterNode := tile_master_blocker.map { _.node := tileBus.node } getOrElse { tileBus.node }
// connect any combination of ITIM, DTIM, and BusErrorUnit
val slaveNode = TLIdentityNode()
DisableMonitors { implicit p =>
val xbarPorts =
scratch.map(lm => (lm.node, xBytes)) ++
busErrorUnit.map(lm => (lm.node, xBytes)) ++
tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes)))
tileParams.icache.flatMap(icache => icache.itimAddr.map(a => (frontend.slaveNode, tileParams.core.fetchBytes))) ++
tile_master_blocker.map( lm => (lm.controlNode, xBytes))
if (xbarPorts.nonEmpty) {
val xbar = LazyModule(new TLXbar)