riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

tile: put a BasicBusBlocker inside RocketTile (#1115)

Browse Source 
...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
This commit is contained in:
Henry Cook
2017-11-17 17:26:48 -08:00
committed by GitHub
parent e7704f46c8
commit b625e68360
6 changed files with 19 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/main/scala/devices/tilelink/BusBlocker.scala
View File

@ -62,8 +62,8 @@ object DevicePMP
case class BusBlockerParams(
controlAddress: BigInt,
controlBeatBytes: Int,
deviceBeatBytes: Int,
pmpRegisters: Int)
deviceBeatBytes: Int = 1, // TODO: This is ignored by the BusBypassBar
pmpRegisters: Int = 1)
{
val page = 4096
val pageBits = log2Ceil(page)
@ -115,7 +115,7 @@ class BusBlocker(params: BusBlockerParams)(implicit p: Parameters) extends TLBus
case class BasicBusBlockerParams(
controlAddress: BigInt,
controlBeatBytes: Int,
deviceBeatBytes: Int,
deviceBeatBytes: Int = 1, // TODO: this is ignored by the BusBypassBar
deadlock: Boolean = false)
class BasicBusBlocker(params: BasicBusBlockerParams)(implicit p: Parameters)