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tile: put a BasicBusBlocker inside RocketTile (#1115)

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...instead of on the master side of the system bus.

People inheriting from HasTileMasterPort might need to add
`masterNode := tileBus.node` to their Tile child class.
This commit is contained in:
Henry Cook
2017-11-17 17:26:48 -08:00
committed by GitHub
parent e7704f46c8
commit b625e68360
6 changed files with 19 additions and 15 deletions
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13
src/main/scala/coreplex/RocketCoreplex.scala
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@ -16,23 +16,16 @@ import freechips.rocketchip.util._
// TODO: how specific are these to RocketTiles?
case class TileMasterPortParams(
addBuffers: Int = 0,
blockerCtrlAddr: Option[BigInt] = None,
cork: Option[Boolean] = None) {
def adapt(coreplex: HasPeripheryBus)
(masterNode: TLOutwardNode)
(implicit p: Parameters, sourceInfo: SourceInfo): TLOutwardNode = {
val tile_master_cork = cork.map(u => (LazyModule(new TLCacheCork(unsafe = u))))
val tile_master_blocker =
blockerCtrlAddr
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes, deadlock = true))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
val tile_master_fixer = LazyModule(new TLFIFOFixer(TLFIFOFixer.allUncacheable))
tile_master_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }
(Seq(tile_master_fixer.node) ++ TLBuffer.chain(addBuffers)
++ tile_master_blocker.map(_.node) ++ tile_master_cork.map(_.node))
.foldRight(masterNode)(_ :=* _)
(Seq(tile_master_fixer.node) ++ TLBuffer.chain(addBuffers) ++ tile_master_cork.map(_.node))
.foldRight(masterNode)(_ :=* _)
}
}
@ -45,7 +38,7 @@ case class TileSlavePortParams(
(implicit p: Parameters, sourceInfo: SourceInfo): TLInwardNode = {
val tile_slave_blocker =
blockerCtrlAddr
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes, coreplex.sbus.beatBytes))
.map(BasicBusBlockerParams(_, coreplex.pbus.beatBytes))
.map(bp => LazyModule(new BasicBusBlocker(bp)))
tile_slave_blocker.foreach { _.controlNode := coreplex.pbus.toVariableWidthSlaves }