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tilelink2 Node: make it possible for {Identity,Output,Input}Node to pass a Vec

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In order to implement a pass-through RAM Monitor model, we will want to support
a variable number of inputs and outputs with BOTH different manager and client
parameters on each bundle.
This commit is contained in:
Wesley W. Terpstra
2016-09-08 21:11:31 -07:00
parent 176f385b1d
commit b587a409a3
3 changed files with 48 additions and 36 deletions
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68
src/main/scala/uncore/tilelink2/Nodes.scala
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@ -29,39 +29,46 @@ class RootNode
}
class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
private val oFn: Option[Seq[PO] => PO],
private val iFn: Option[Seq[PI] => PI],
private val oFn: (Int, Seq[PO]) => Seq[PO],
private val iFn: (Int, Seq[PI]) => Seq[PI],
private val numPO: Range.Inclusive,
private val numPI: Range.Inclusive) extends RootNode
{
// At least 0 ports must be supported
require (!numPO.isEmpty)
require (!numPI.isEmpty)
require (numPO.start >= 0)
require (numPI.start >= 0)
def name = lazyModule.name + "." + getClass.getName.split('.').last
require (!numPO.isEmpty, s"No number of outputs would be acceptable to ${name}${lazyModule.line}")
require (!numPI.isEmpty, s"No number of inputs would be acceptable to ${name}${lazyModule.line}")
require (numPO.start >= 0, s"${name} accepts a negative number of outputs${lazyModule.line}")
require (numPI.start >= 0, s"${name} accepts a negative number of inputs${lazyModule.line}")
val noOs = numPO.size == 1 && numPO.contains(0)
val noIs = numPI.size == 1 && numPI.contains(0)
require (noOs || oFn.isDefined)
require (noIs || iFn.isDefined)
private val accPO = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
private val accPI = ListBuffer[BaseNode[PO, PI, EO, EI, B]]()
private val accPO = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
private val accPI = ListBuffer[(Int, BaseNode[PO, PI, EO, EI, B])]()
private var oRealized = false
private var iRealized = false
def name = lazyModule.name + "." + getClass.getName.split('.').last
private def reqO() = require(numPO.contains(accPO.size), s"${name} has ${accPO.size} outputs, expected ${numPO}${lazyModule.line}")
private def reqI() = require(numPI.contains(accPI.size), s"${name} has ${accPI.size} inputs, expected ${numPI}${lazyModule.line}")
protected def reqE(o: Int, i: Int) = require(i == o, s"${name} has ${i} inputs and ${o} outputs; they must match${lazyModule.line}")
private lazy val oPorts = { oRealized = true; reqO(); accPO.result() }
private lazy val iPorts = { iRealized = true; reqI(); accPI.result() }
private lazy val oParams : Option[PO] = oFn.map(_(iPorts.map(_.oParams.get)))
private lazy val iParams : Option[PI] = iFn.map(_(oPorts.map(_.iParams.get)))
lazy val edgesOut = oPorts.map { n => imp.edgeO(oParams.get, n.iParams.get) }
lazy val edgesIn = iPorts.map { n => imp.edgeI(n.oParams.get, iParams.get) }
private lazy val oParams : Seq[PO] = {
val o = oFn(oPorts.size, iPorts.map{ case (i, n) => n.oParams(i) })
reqE(oPorts.size, o.size)
o
}
private lazy val iParams : Seq[PI] = {
val i = iFn(iPorts.size, oPorts.map{ case (o, n) => n.iParams(o) })
reqE(i.size, iPorts.size)
i
}
lazy val edgesOut = (oPorts zip oParams).map { case ((i, n), o) => imp.edgeO(o, n.iParams(i)) }
lazy val edgesIn = (iPorts zip iParams).map { case ((o, n), i) => imp.edgeI(n.oParams(o), i) }
lazy val bundleOut = imp.bundleO(edgesOut)
lazy val bundleIn = imp.bundleI(edgesIn)
@ -71,14 +78,15 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
// source.edge(sink)
protected[tilelink2] def edge(x: BaseNode[PO, PI, EO, EI, B])(implicit sourceInfo: SourceInfo) = {
require (!noOs)
require (!oRealized)
require (!x.noIs)
require (!x.iRealized)
val info = sourceLine(sourceInfo, " at ", "")
require (!noOs, s"${name}${lazyModule.line} was incorrectly connected as a source" + info)
require (!oRealized, s"${name}${lazyModule.line} was incorrectly connected as a source after it's .module was used" + info)
require (!x.noIs, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink" + info)
require (!x.iRealized, s"${x.name}${x.lazyModule.line} was incorrectly connected as a sink after it's .module was used" + info)
val i = x.accPI.size
val o = accPO.size
accPO += x
x.accPI += this
accPO += ((i, x))
x.accPI += ((o, this))
() => {
imp.connect(connectOut(o), edgesOut(o), x.connectIn(i), x.edgesIn(i))
}
@ -86,7 +94,7 @@ class BaseNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(
}
class IdentityNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
extends BaseNode(imp)(Some{case Seq(x) => x}, Some{case Seq(x) => x}, 1 to 1, 1 to 1)
extends BaseNode(imp)({case (_, s) => s}, {case (_, s) => s}, 0 to 999, 0 to 999)
class OutputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) extends IdentityNode(imp)
{
@ -101,21 +109,21 @@ class InputNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B]) exte
}
class SourceNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(po: PO, num: Range.Inclusive = 1 to 1)
extends BaseNode(imp)(Some{case Seq() => po}, None, num, 0 to 0)
extends BaseNode(imp)({case (n, Seq()) => Seq.fill(n)(po)}, {case (0, _) => Seq()}, num, 0 to 0)
{
require (num.end >= 1)
require (num.end >= 1, s"${name} is a source which does not accept outputs${lazyModule.line}")
}
class SinkNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])(pi: PI, num: Range.Inclusive = 1 to 1)
extends BaseNode(imp)(None, Some{case Seq() => pi}, 0 to 0, num)
extends BaseNode(imp)({case (0, _) => Seq()}, {case (n, Seq()) => Seq.fill(n)(pi)}, 0 to 0, num)
{
require (num.end >= 1)
require (num.end >= 1, s"${name} is a sink which does not accept inputs${lazyModule.line}")
}
class InteriorNode[PO, PI, EO, EI, B <: Data](imp: NodeImp[PO, PI, EO, EI, B])
(oFn: Seq[PO] => PO, iFn: Seq[PI] => PI, numPO: Range.Inclusive, numPI: Range.Inclusive)
extends BaseNode(imp)(Some(oFn), Some(iFn), numPO, numPI)
extends BaseNode(imp)({case (n,s) => Seq.fill(n)(oFn(s))}, {case (n,s) => Seq.fill(n)(iFn(s))}, numPO, numPI)
{
require (numPO.end >= 1)
require (numPI.end >= 1)
require (numPO.end >= 1, s"${name} is an adapter which does not accept outputs${lazyModule.line}")
require (numPI.end >= 1, s"${name} is an adapter which does not accept inputs${lazyModule.line}")
}