riscv/rocket-chip
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don't use splat and bug out if too many address map entries

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This commit is contained in:
Howard Mao 2016-07-11 18:10:42 -07:00
parent 46fc9744e2
commit b47f8fbc41
2 changed files with 2 additions and 2 deletions
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2
src/main/scala/Configs.scala
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@ -39,7 +39,7 @@ class BaseConfig extends Config (
lazy val globalAddrMap = { lazy val globalAddrMap = {
val memBase = 0x80000000L val memBase = 0x80000000L
val memSize = 0x10000000L val memSize = 0x10000000L
val io = AddrMap((AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries):_*) val io = new AddrMap(AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries)
val addrMap = AddrMap( val addrMap = AddrMap(
AddrMapEntry("io", io), AddrMapEntry("io", io),
AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))) AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))

2
src/main/scala/RocketChip.scala
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@ -251,7 +251,7 @@ class Uncore(implicit val p: Parameters) extends Module
} else if (mmio_tl_start <= i && i < mmio_tl_end) { } else if (mmio_tl_start <= i && i < mmio_tl_end) {
TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i)) TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i))
} else { } else {
TopUtils.connectTilelinkNasti(Module(new NastiErrorSlave).io, ports(i)) require(false, "Unconnected external MMIO port")
} }
} }
} }