diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala
index cac8d392..4a81c64a 100644
--- a/src/main/scala/Configs.scala
+++ b/src/main/scala/Configs.scala
@@ -39,7 +39,7 @@ class BaseConfig extends Config (
     lazy val globalAddrMap = {
       val memBase = 0x80000000L
       val memSize = 0x10000000L
-      val io = AddrMap((AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries):_*)
+      val io = new AddrMap(AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries)
       val addrMap = AddrMap(
         AddrMapEntry("io", io),
         AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true))))
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index b7a508e4..aeb8f44b 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -251,7 +251,7 @@ class Uncore(implicit val p: Parameters) extends Module
       } else if (mmio_tl_start <= i && i < mmio_tl_end) {
         TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i))
       } else {
-        TopUtils.connectTilelinkNasti(Module(new NastiErrorSlave).io, ports(i))
+        require(false, "Unconnected external MMIO port")
       }
     }
   }