From b47f8fbc41befbdd08eadbe064aa937137d5f5c3 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 11 Jul 2016 18:10:42 -0700 Subject: [PATCH] don't use splat and bug out if too many address map entries --- src/main/scala/Configs.scala | 2 +- src/main/scala/RocketChip.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/Configs.scala b/src/main/scala/Configs.scala index cac8d392..4a81c64a 100644 --- a/src/main/scala/Configs.scala +++ b/src/main/scala/Configs.scala @@ -39,7 +39,7 @@ class BaseConfig extends Config ( lazy val globalAddrMap = { val memBase = 0x80000000L val memSize = 0x10000000L - val io = AddrMap((AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries):_*) + val io = new AddrMap(AddrMapEntry("int", internalIOAddrMap) +: site(ExtMMIOPorts).entries) val addrMap = AddrMap( AddrMapEntry("io", io), AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index b7a508e4..aeb8f44b 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -251,7 +251,7 @@ class Uncore(implicit val p: Parameters) extends Module } else if (mmio_tl_start <= i && i < mmio_tl_end) { TopUtils.connectTilelink(io.mmio_tl(i-mmio_tl_start), ports(i)) } else { - TopUtils.connectTilelinkNasti(Module(new NastiErrorSlave).io, ports(i)) + require(false, "Unconnected external MMIO port") } } }