riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

axi4: ToTL supporting pipelined MMIO

Browse Source
This commit is contained in:
Wesley W. Terpstra committed 2017-05-01 22:53:40 -07:00
1 parent ca2cb033cd
commit b4188ee625
2 files changed
+68 -82
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/coreplex/CoreplexNetwork.scala
+3 -1
View File
@@ -32,7 +32,9 @@ trait CoreplexNetwork extends HasCoreplexParameters {
// Allows a variable number of inputs from outside to the Xbar
private val l2in_buffer = LazyModule(new TLBuffer)
l1tol2.node :=* l2in_buffer.node
private val l2in_fifo = LazyModule(new TLFIFOFixer)
l1tol2.node :=* l2in_fifo.node
l2in_fifo.node :=* l2in_buffer.node
l2in_buffer.node :=* l2in
private val l2out_buffer = LazyModule(new TLBuffer(BufferParams.flow, BufferParams.none))