riscv/rocket-chip
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sret bugfix: bypass arbiter

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This commit is contained in:
Henry Cook 2015-03-05 13:14:16 -08:00
parent 35532420a8
commit b36d751250
2 changed files with 2 additions and 0 deletions
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1
rocket/src/main/scala/rocc.scala
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@ -121,6 +121,7 @@ class AccumulatorExample extends RoCC
io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores) io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores)
io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1 io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1
io.mem.req.bits.data := Bits(0) // we're not performing any stores... io.mem.req.bits.data := Bits(0) // we're not performing any stores...
io.mem.sret := false
io.imem.acquire.valid := false io.imem.acquire.valid := false
io.imem.grant.ready := false io.imem.grant.ready := false

1
rocket/src/main/scala/tile.scala
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@ -26,6 +26,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
val ptw = Module(new PTW(params(NPTWPorts))) val ptw = Module(new PTW(params(NPTWPorts)))
val core = Module(new Core, { case CoreName => "Rocket" }) val core = Module(new Core, { case CoreName => "Rocket" })
dcache.io.cpu.sret := core.io.dmem.sret
val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts))) val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
dcArb.io.requestor(0) <> ptw.io.mem dcArb.io.requestor(0) <> ptw.io.mem
dcArb.io.requestor(1) <> core.io.dmem dcArb.io.requestor(1) <> core.io.dmem