From b36d751250730e13b9c56a7fd0faeeead7e07e26 Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Thu, 5 Mar 2015 13:14:16 -0800 Subject: [PATCH] sret bugfix: bypass arbiter --- rocket/src/main/scala/rocc.scala | 1 + rocket/src/main/scala/tile.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/rocket/src/main/scala/rocc.scala b/rocket/src/main/scala/rocc.scala index 49d8d332..425c96b5 100644 --- a/rocket/src/main/scala/rocc.scala +++ b/rocket/src/main/scala/rocc.scala @@ -121,6 +121,7 @@ class AccumulatorExample extends RoCC io.mem.req.bits.cmd := M_XRD // perform a load (M_XWR for stores) io.mem.req.bits.typ := MT_D // D = 8 bytes, W = 4, H = 2, B = 1 io.mem.req.bits.data := Bits(0) // we're not performing any stores... + io.mem.sret := false io.imem.acquire.valid := false io.imem.grant.ready := false diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala index de188bdf..bb5356ee 100644 --- a/rocket/src/main/scala/tile.scala +++ b/rocket/src/main/scala/tile.scala @@ -26,6 +26,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) { val ptw = Module(new PTW(params(NPTWPorts))) val core = Module(new Core, { case CoreName => "Rocket" }) + dcache.io.cpu.sret := core.io.dmem.sret val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts))) dcArb.io.requestor(0) <> ptw.io.mem dcArb.io.requestor(1) <> core.io.dmem