sret bugfix: bypass arbiter

2015-03-05 13:14:16 -08:00
parent 35532420a8
commit b36d751250
2 changed files with 2 additions and 0 deletions
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@ -26,6 +26,7 @@ class RocketTile(resetSignal: Bool = null) extends Tile(resetSignal) {
  val ptw = Module(new PTW(params(NPTWPorts)))
  val core = Module(new Core, { case CoreName => "Rocket" })

+  dcache.io.cpu.sret := core.io.dmem.sret
  val dcArb = Module(new HellaCacheArbiter(params(NDCachePorts)))
  dcArb.io.requestor(0) <> ptw.io.mem
  dcArb.io.requestor(1) <> core.io.dmem