riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

add option to log L2 cache transactions for easier debugging

Browse Source
This commit is contained in:
Howard Mao 2016-07-06 14:59:09 -07:00
parent 64afc795fd
commit b10d306b4a
1 changed files with 16 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

17
uncore/src/main/scala/agents/Trackers.scala
View File

@ -6,9 +6,11 @@ import Chisel._
import uncore.coherence._ import uncore.coherence._
import uncore.tilelink._ import uncore.tilelink._
import uncore.util._ import uncore.util._
import cde.Parameters import cde.{Field, Parameters}
import scala.math.max import scala.math.max
case object EnableL2Logging extends Field[Boolean]
class TrackerAllocation extends Bundle { class TrackerAllocation extends Bundle {
val matches = Bool(OUTPUT) val matches = Bool(OUTPUT)
val can = Bool(OUTPUT) val can = Bool(OUTPUT)
@ -265,6 +267,12 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer {
} .otherwise { } .otherwise {
pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release)) pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release))
} }
if (p(EnableL2Logging)) {
when (io.irel().hasData()) {
printf("[release] addr_block=%x addr_beat=%d data=%x\n",
io.irel().addr_block, io.irel().addr_beat, io.irel().data)
}
}
} }
io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) && io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) &&
@ -486,6 +494,13 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
add_pending_bits add_pending_bits
} }
if (p(EnableL2Logging)) {
when (io.inner.grant.fire() && io.ignt().hasData()) {
printf("[get] addr_block=%x addr_beat=%d data=%x\n",
xact_addr_block, io.ignt().addr_beat, io.ignt().data)
}
}
// Have we finished receiving the complete inner acquire transaction? // Have we finished receiving the complete inner acquire transaction?
val iacq_finished = !(state === s_idle || val iacq_finished = !(state === s_idle ||
state === s_meta_read || state === s_meta_read ||