From b10d306b4ad3e3d99428c42923cf2ba196fcfa50 Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Wed, 6 Jul 2016 14:59:09 -0700 Subject: [PATCH] add option to log L2 cache transactions for easier debugging --- uncore/src/main/scala/agents/Trackers.scala | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/uncore/src/main/scala/agents/Trackers.scala b/uncore/src/main/scala/agents/Trackers.scala index bf7c7b7a..3db62194 100644 --- a/uncore/src/main/scala/agents/Trackers.scala +++ b/uncore/src/main/scala/agents/Trackers.scala @@ -6,9 +6,11 @@ import Chisel._ import uncore.coherence._ import uncore.tilelink._ import uncore.util._ -import cde.Parameters +import cde.{Field, Parameters} import scala.math.max +case object EnableL2Logging extends Field[Boolean] + class TrackerAllocation extends Bundle { val matches = Bool(OUTPUT) val can = Bool(OUTPUT) @@ -265,6 +267,12 @@ trait AcceptsVoluntaryReleases extends HasVoluntaryReleaseMetadataBuffer { } .otherwise { pending_irel_data := (pending_irel_data & dropPendingBitWhenBeatHasData(io.inner.release)) } + if (p(EnableL2Logging)) { + when (io.irel().hasData()) { + printf("[release] addr_block=%x addr_beat=%d data=%x\n", + io.irel().addr_block, io.irel().addr_beat, io.irel().data) + } + } } io.inner.grant.valid := Vec(s_wb_req, s_wb_resp, s_inner_probe, s_busy).contains(state) && @@ -486,6 +494,13 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer add_pending_bits } + if (p(EnableL2Logging)) { + when (io.inner.grant.fire() && io.ignt().hasData()) { + printf("[get] addr_block=%x addr_beat=%d data=%x\n", + xact_addr_block, io.ignt().addr_beat, io.ignt().data) + } + } + // Have we finished receiving the complete inner acquire transaction? val iacq_finished = !(state === s_idle || state === s_meta_read ||