From b040a462c955cc18084df0cc0d2b8d07bb985594 Mon Sep 17 00:00:00 2001 From: Scott Johnson Date: Wed, 26 Apr 2017 16:46:57 -0700 Subject: [PATCH] Wes's change to remove user bits from external AXI interface, and add 1 cycle latency to make sure external AXI is compliant --- src/main/scala/uncore/axi4/Test.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/axi4/Test.scala b/src/main/scala/uncore/axi4/Test.scala index 2e75d370..69c97580 100644 --- a/src/main/scala/uncore/axi4/Test.scala +++ b/src/main/scala/uncore/axi4/Test.scala @@ -70,13 +70,13 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule model.node := fuzz.node node := - // AXI4UserYanker()( ... once TLToAXI is updated + AXI4UserYanker()( AXI4Deinterleaver(64)( TLToAXI4(4)( TLDelayer(0.1)( TLBuffer(BufferParams.flow)( TLDelayer(0.1)( - model.node))))) + model.node)))))) lazy val module = new LazyModuleImp(this) { val io = new Bundle { @@ -92,7 +92,7 @@ class AXI4FuzzSlave()(implicit p: Parameters) extends LazyModule { val node = AXI4InputNode() val xbar = LazyModule(new TLXbar) - val ram = LazyModule(new TLTestRAM(AddressSet(0x0, 0xfff))) + val ram = LazyModule(new TLRAM(AddressSet(0x0, 0xfff))) val error= LazyModule(new TLError(Seq(AddressSet(0x1800, 0xff)))) ram.node := TLFragmenter(4, 16)(xbar.node)