diff --git a/src/main/scala/rocketchip/Configs.scala b/src/main/scala/rocketchip/Configs.scala
index 5a6453ec..72c72631 100644
--- a/src/main/scala/rocketchip/Configs.scala
+++ b/src/main/scala/rocketchip/Configs.scala
@@ -154,7 +154,7 @@ class BasePlatformConfig extends Config (
       case ConfigString => makeConfigString()
       case GlobalAddrMap => globalAddrMap
       case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
-      case RTC => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc() 
+      case RTCTick => (p: Parameters, t_io: Bundle, p_io:Bundle) => Counter(p(RTCPeriod)).inc() 
       case _ => throw new CDEMatchError
   }})
 
diff --git a/src/main/scala/rocketchip/RocketChip.scala b/src/main/scala/rocketchip/RocketChip.scala
index 5990c8cd..3a356f47 100644
--- a/src/main/scala/rocketchip/RocketChip.scala
+++ b/src/main/scala/rocketchip/RocketChip.scala
@@ -54,7 +54,7 @@ case object ExtMemSize extends Field[Long]
 case object NExtTopInterrupts extends Field[Int]
 case object NExtPeripheryInterrupts extends Field[Int]
 /** Source of  RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra  **/
-case object RTC extends Field[(Parameters, Bundle, Bundle) => Bool]
+case object RTCTick extends Field[(Parameters, Bundle, Bundle) => Bool]
 case object RTCPeriod extends Field[Int]
 
 
@@ -199,12 +199,13 @@ class Top(topParams: Parameters) extends Module with HasTopLevelParameters {
 
   io.extra <> periphery.io.extra
 
-  coreplex.io.rtcTick := p(RTC)(p, io.extra, periphery.io.extra)
+  coreplex.io.rtcTick := p(RTCTick)(p, io.extra, periphery.io.extra)
 
   p(ConnectExtraPorts)(io.extra, coreplex.io.extra, p)
 
 }
 
+
 class Periphery(implicit val p: Parameters) extends Module
     with HasTopLevelParameters {
   val io = new Bundle {