riscv/rocket-chip
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2

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Conflicts:
	src/core.scala
	src/ctrl.scala
	src/dpath_util.scala
	src/fpu.scala
	src/nbdcache.scala
	src/tile.scala
This commit is contained in:
Henry Cook
2013-08-15 16:35:27 -07:00
parent 3a266cbbfa 387cf0ebe0
commit ae02ebd153
3 changed files with 3 additions and 3 deletions
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2
rocket/src/main/scala/core.scala
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@@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
} else null } else null
if (conf.vec) { if (conf.vec) {
val vu = Module(new vu(Reg(next=reset))) val vu = Module(new vu(Reg(next=this.reset)))
val vdtlb = Module(new TLB(8)) val vdtlb = Module(new TLB(8))
ptw += vdtlb.io.ptw ptw += vdtlb.io.ptw

2
rocket/src/main/scala/dpath_util.scala
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@@ -278,7 +278,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
io.host.ipi_rep.ready := Bool(true) io.host.ipi_rep.ready := Bool(true)
when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) } when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
when(reset) { when(this.reset) {
reg_status.et := false reg_status.et := false
reg_status.ef := false reg_status.ef := false
reg_status.ev := false reg_status.ev := false

2
rocket/src/main/scala/tile.scala
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@@ -19,7 +19,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
if (fastLoadByte) require(fastLoadWord) if (fastLoadByte) require(fastLoadWord)
} }
class Tile(_reset: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = _reset) with ClientCoherenceAgent class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
{ {
val memPorts = 2 + confIn.vec val memPorts = 2 + confIn.vec
val dcachePortId = 0 val dcachePortId = 0