diff --git a/rocket/src/main/scala/core.scala b/rocket/src/main/scala/core.scala
index 788e18dc..56e4f0aa 100644
--- a/rocket/src/main/scala/core.scala
+++ b/rocket/src/main/scala/core.scala
@@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
   } else null
 
   if (conf.vec) {
-    val vu = Module(new vu(Reg(next=reset)))
+    val vu = Module(new vu(Reg(next=this.reset)))
 
     val vdtlb = Module(new TLB(8))
     ptw += vdtlb.io.ptw
diff --git a/rocket/src/main/scala/dpath_util.scala b/rocket/src/main/scala/dpath_util.scala
index 40ae0e14..4aae4679 100644
--- a/rocket/src/main/scala/dpath_util.scala
+++ b/rocket/src/main/scala/dpath_util.scala
@@ -278,7 +278,7 @@ class PCR(implicit conf: RocketConfiguration) extends Module
   io.host.ipi_rep.ready := Bool(true)
   when (io.host.ipi_rep.valid) { r_irq_ipi := Bool(true) }
 
-  when(reset) {
+  when(this.reset) {
     reg_status.et := false
     reg_status.ef := false
     reg_status.ev := false
diff --git a/rocket/src/main/scala/tile.scala b/rocket/src/main/scala/tile.scala
index b998fc6e..c83be474 100644
--- a/rocket/src/main/scala/tile.scala
+++ b/rocket/src/main/scala/tile.scala
@@ -19,7 +19,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
   if (fastLoadByte) require(fastLoadWord)
 }
 
-class Tile(_reset: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = _reset) with ClientCoherenceAgent
+class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
 {
   val memPorts = 2 + confIn.vec
   val dcachePortId = 0