riscv/rocket-chip
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Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2

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Conflicts:
	src/core.scala
	src/ctrl.scala
	src/dpath_util.scala
	src/fpu.scala
	src/nbdcache.scala
	src/tile.scala
This commit is contained in:
Henry Cook
2013-08-15 16:35:27 -07:00
parent 3a266cbbfa 387cf0ebe0
commit ae02ebd153
3 changed files with 3 additions and 3 deletions
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2
rocket/src/main/scala/tile.scala
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@ -19,7 +19,7 @@ case class RocketConfiguration(tl: TileLinkConfiguration,
if (fastLoadByte) require(fastLoadWord)
}
class Tile(_reset: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = _reset) with ClientCoherenceAgent
class Tile(resetSignal: Bool = null)(confIn: RocketConfiguration) extends Module(_reset = resetSignal) with ClientCoherenceAgent
{
val memPorts = 2 + confIn.vec
val dcachePortId = 0