Merge branch 'chisel-v2' of github.com:ucb-bar/riscv-rocket into chisel-v2

Conflicts:
	src/core.scala
	src/ctrl.scala
	src/dpath_util.scala
	src/fpu.scala
	src/nbdcache.scala
	src/tile.scala

rocket/src/main/scala/core.scala

@@ -42,7 +42,7 @@ class Core(implicit conf: RocketConfiguration) extends Module
   } else null
 
   if (conf.vec) {
-    val vu = Module(new vu(Reg(next=reset)))
+    val vu = Module(new vu(Reg(next=this.reset)))
 
     val vdtlb = Module(new TLB(8))
     ptw += vdtlb.io.ptw