riscv/rocket-chip
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Use ROMs to reduce node count and improve QoR a bit

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This commit is contained in:
Andrew Waterman 2014-05-25 23:58:53 -07:00
parent 88899eafe0
commit ac88ded35a
2 changed files with 6 additions and 7 deletions
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10
rocket/src/main/scala/csr.scala
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@ -109,14 +109,12 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500) val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
val decoded_addr = { val decoded_addr = {
val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size)) val map = for ((v, i) <- CSRs.all.zipWithIndex)
val outs = for (i <- 0 until CSRs.all.size) yield v -> UInt(BigInt(1) << i)
yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size)) val out = ROM(map)(addr)
val d = DecodeLogic(addr, default, outs).toArray
val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool]) val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
for (i <- 0 until CSRs.all.size) for (i <- 0 until CSRs.all.size)
a(CSRs.all(i)) = d(0)(i) a(CSRs.all(i)) = out(i)
a a
} }

3
rocket/src/main/scala/ctrl.scala
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@ -421,10 +421,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
legal_csrs --= fp_csrs legal_csrs --= fp_csrs
val id_csr_addr = io.dpath.inst(31,20) val id_csr_addr = io.dpath.inst(31,20)
val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i))
val id_csr_en = id_csr != CSR.N val id_csr_en = id_csr != CSR.N
val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr) val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr) val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr)
val id_csr_privileged = id_csr_en && val id_csr_privileged = id_csr_en &&
(id_csr_addr(11,10) === UInt(3) && id_csr_wen || (id_csr_addr(11,10) === UInt(3) && id_csr_wen ||
id_csr_addr(11,10) === UInt(2) || id_csr_addr(11,10) === UInt(2) ||