From ac88ded35ae03860c9187a77023e7174a2148743 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Sun, 25 May 2014 23:58:53 -0700 Subject: [PATCH] Use ROMs to reduce node count and improve QoR a bit --- rocket/src/main/scala/csr.scala | 10 ++++------ rocket/src/main/scala/ctrl.scala | 3 ++- 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/rocket/src/main/scala/csr.scala b/rocket/src/main/scala/csr.scala index 2169055b..9d62ba44 100644 --- a/rocket/src/main/scala/csr.scala +++ b/rocket/src/main/scala/csr.scala @@ -109,14 +109,12 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500) val decoded_addr = { - val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size)) - val outs = for (i <- 0 until CSRs.all.size) - yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size)) - - val d = DecodeLogic(addr, default, outs).toArray + val map = for ((v, i) <- CSRs.all.zipWithIndex) + yield v -> UInt(BigInt(1) << i) + val out = ROM(map)(addr) val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool]) for (i <- 0 until CSRs.all.size) - a(CSRs.all(i)) = d(0)(i) + a(CSRs.all(i)) = out(i) a } diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 6148fcf4..c6fb932f 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -421,10 +421,11 @@ class Control(implicit conf: RocketConfiguration) extends Module legal_csrs --= fp_csrs val id_csr_addr = io.dpath.inst(31,20) + val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i)) val id_csr_en = id_csr != CSR.N val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs) val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr) - val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr) + val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr) val id_csr_privileged = id_csr_en && (id_csr_addr(11,10) === UInt(3) && id_csr_wen || id_csr_addr(11,10) === UInt(2) ||