riscv/rocket-chip
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Use ROMs to reduce node count and improve QoR a bit

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Andrew Waterman committed 2014-06-14 13:58:07 -07:00
1 parent 88899eafe0
commit ac88ded35a
2 files changed
+6 -7
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rocket/src/main/scala/ctrl.scala
+2 -1
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@@ -421,10 +421,11 @@ class Control(implicit conf: RocketConfiguration) extends Module
legal_csrs --= fp_csrs
val id_csr_addr = io.dpath.inst(31,20)
val isLegalCSR = Vec.tabulate(1 << id_csr_addr.getWidth)(i => Bool(legal_csrs contains i))
val id_csr_en = id_csr != CSR.N
val id_csr_fp = Bool(!conf.fpu.isEmpty) && id_csr_en && DecodeLogic(id_csr_addr, fp_csrs, CSRs.all.toSet -- fp_csrs)
val id_csr_wen = id_raddr1 != UInt(0) || !Vec(CSR.S, CSR.C).contains(id_csr)
val id_csr_invalid = id_csr_en && !Vec(legal_csrs.map(UInt(_))).contains(id_csr_addr)
val id_csr_invalid = id_csr_en && !isLegalCSR(id_csr_addr)
val id_csr_privileged = id_csr_en &&
(id_csr_addr(11,10) === UInt(3) && id_csr_wen ||
id_csr_addr(11,10) === UInt(2) ||