riscv/rocket-chip
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Use ROMs to reduce node count and improve QoR a bit

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This commit is contained in:
Andrew Waterman
2014-05-25 23:58:53 -07:00
parent 88899eafe0
commit ac88ded35a
2 changed files with 6 additions and 7 deletions
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10
rocket/src/main/scala/csr.scala
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@ -109,14 +109,12 @@ class CSRFile(implicit conf: RocketConfiguration) extends Module
val addr = Mux(cpu_req_valid, io.rw.addr, host_pcr_bits.addr | 0x500)
val decoded_addr = {
val default = List(Bits("b" + ("?"*CSRs.all.size), CSRs.all.size))
val outs = for (i <- 0 until CSRs.all.size)
yield UInt(CSRs.all(i), addr.getWidth) -> List(UInt(BigInt(1) << i, CSRs.all.size))
val d = DecodeLogic(addr, default, outs).toArray
val map = for ((v, i) <- CSRs.all.zipWithIndex)
yield v -> UInt(BigInt(1) << i)
val out = ROM(map)(addr)
val a = Array.fill(CSRs.all.max+1)(null.asInstanceOf[Bool])
for (i <- 0 until CSRs.all.size)
a(CSRs.all(i)) = d(0)(i)
a(CSRs.all(i)) = out(i)
a
}