Move microarchitecture-neutral params from Rocket to Core

This makes some of the units more reusable.

src/main/scala/tile/Core.scala

@@ -25,7 +25,12 @@ trait CoreParams {
   val retireWidth: Int
   val instBits: Int
   val nLocalInterrupts: Int
+  val nPMPs: Int
+  val nBreakpoints: Int
+  val nPerfCounters: Int
   val nL2TLBEntries: Int
+  val mtvecInit: Option[BigInt]
+  val mtvecWritable: Boolean
   val jumpInFrontend: Boolean
   val tileControlAddr: Option[BigInt]
 
@@ -53,6 +58,12 @@ trait HasCoreParameters extends HasTileParameters {
   val coreDataBytes = coreDataBits/8
   val coreMaxAddrBits = paddrBits max vaddrBitsExtended
 
+  val nBreakpoints = coreParams.nBreakpoints
+  val nPMPs = coreParams.nPMPs
+  val nPerfCounters = coreParams.nPerfCounters
+  val mtvecInit = coreParams.mtvecInit
+  val mtvecWritable = coreParams.mtvecWritable
+
   val coreDCacheReqTagBits = 6
   val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)