From ab0821f25b1ceadb40ae58b8e6744963beeeb320 Mon Sep 17 00:00:00 2001
From: Andrew Waterman <andrew@sifive.com>
Date: Wed, 20 Sep 2017 14:04:13 -0700
Subject: [PATCH] Move microarchitecture-neutral params from Rocket to Core

This makes some of the units more reusable.
---
 src/main/scala/rocket/CSR.scala        |  8 ++++----
 src/main/scala/rocket/PMP.scala        |  2 +-
 src/main/scala/rocket/PTW.scala        |  4 ++--
 src/main/scala/rocket/RocketCore.scala |  5 -----
 src/main/scala/tile/Core.scala         | 11 +++++++++++
 5 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index a8371c0b..989b665a 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -63,7 +63,7 @@ class DCSR extends Bundle {
 }
 
 class MIP(implicit p: Parameters) extends CoreBundle()(p)
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val lip = Vec(coreParams.nLocalInterrupts, Bool())
   val zero2 = Bool()
   val debug = Bool() // keep in sync with CSR.debugIntCause
@@ -144,7 +144,7 @@ object CSR
 }
 
 class PerfCounterIO(implicit p: Parameters) extends CoreBundle
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val eventSel = UInt(OUTPUT, xLen)
   val inc = UInt(INPUT, log2Ceil(1+retireWidth))
 }
@@ -161,7 +161,7 @@ class TracedInstruction(implicit p: Parameters) extends CoreBundle {
 }
 
 class CSRFileIO(implicit p: Parameters) extends CoreBundle
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val interrupts = new TileInterrupts().asInput
   val hartid = UInt(INPUT, hartIdLen)
   val rw = new Bundle {
@@ -207,7 +207,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
 }
 
 class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Parameters) extends CoreModule()(p)
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val io = new CSRFileIO
 
   val reset_mstatus = Wire(init=new MStatus().fromBits(0))
diff --git a/src/main/scala/rocket/PMP.scala b/src/main/scala/rocket/PMP.scala
index 2e277a77..02d69aab 100644
--- a/src/main/scala/rocket/PMP.scala
+++ b/src/main/scala/rocket/PMP.scala
@@ -127,7 +127,7 @@ class PMPHomogeneityChecker(pmps: Seq[PMP])(implicit p: Parameters) {
 }
 
 class PMPChecker(lgMaxSize: Int)(implicit p: Parameters) extends CoreModule()(p)
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val io = new Bundle {
     val prv = UInt(INPUT, PRV.SZ)
     val pmp = Vec(nPMPs, new PMP).asInput
diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala
index 4618715f..70ec7b12 100644
--- a/src/main/scala/rocket/PTW.scala
+++ b/src/main/scala/rocket/PTW.scala
@@ -24,7 +24,7 @@ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
 }
 
 class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val req = Decoupled(new PTWReq)
   val resp = Valid(new PTWResp).flip
   val ptbr = new PTBR().asInput
@@ -37,7 +37,7 @@ class PTWPerfEvents extends Bundle {
 }
 
 class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
-    with HasRocketCoreParameters {
+    with HasCoreParameters {
   val ptbr = new PTBR().asInput
   val sfence = Valid(new SFenceReq).flip
   val status = new MStatus().asInput
diff --git a/src/main/scala/rocket/RocketCore.scala b/src/main/scala/rocket/RocketCore.scala
index ae0d251b..9e010def 100644
--- a/src/main/scala/rocket/RocketCore.scala
+++ b/src/main/scala/rocket/RocketCore.scala
@@ -45,11 +45,6 @@ trait HasRocketCoreParameters extends HasCoreParameters {
 
   val fastLoadWord = rocketParams.fastLoadWord
   val fastLoadByte = rocketParams.fastLoadByte
-  val nBreakpoints = rocketParams.nBreakpoints
-  val nPMPs = rocketParams.nPMPs
-  val nPerfCounters = rocketParams.nPerfCounters
-  val mtvecInit = rocketParams.mtvecInit
-  val mtvecWritable = rocketParams.mtvecWritable
 
   val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this
 
diff --git a/src/main/scala/tile/Core.scala b/src/main/scala/tile/Core.scala
index da400df9..9decc107 100644
--- a/src/main/scala/tile/Core.scala
+++ b/src/main/scala/tile/Core.scala
@@ -25,7 +25,12 @@ trait CoreParams {
   val retireWidth: Int
   val instBits: Int
   val nLocalInterrupts: Int
+  val nPMPs: Int
+  val nBreakpoints: Int
+  val nPerfCounters: Int
   val nL2TLBEntries: Int
+  val mtvecInit: Option[BigInt]
+  val mtvecWritable: Boolean
   val jumpInFrontend: Boolean
   val tileControlAddr: Option[BigInt]
 
@@ -53,6 +58,12 @@ trait HasCoreParameters extends HasTileParameters {
   val coreDataBytes = coreDataBits/8
   val coreMaxAddrBits = paddrBits max vaddrBitsExtended
 
+  val nBreakpoints = coreParams.nBreakpoints
+  val nPMPs = coreParams.nPMPs
+  val nPerfCounters = coreParams.nPerfCounters
+  val mtvecInit = coreParams.mtvecInit
+  val mtvecWritable = coreParams.mtvecWritable
+
   val coreDCacheReqTagBits = 6
   val dcacheReqTagBits = coreDCacheReqTagBits + log2Ceil(dcacheArbPorts)