riscv/rocket-chip
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Move microarchitecture-neutral params from Rocket to Core

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This makes some of the units more reusable.
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Andrew Waterman committed 2017-10-03 17:34:18 -07:00
1 parent 190d5c50d9
commit ab0821f25b
5 files changed
+18 -12
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src/main/scala/rocket/RocketCore.scala
-5
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@@ -45,11 +45,6 @@ trait HasRocketCoreParameters extends HasCoreParameters {
val fastLoadWord = rocketParams.fastLoadWord
val fastLoadByte = rocketParams.fastLoadByte
val nBreakpoints = rocketParams.nBreakpoints
val nPMPs = rocketParams.nPMPs
val nPerfCounters = rocketParams.nPerfCounters
val mtvecInit = rocketParams.mtvecInit
val mtvecWritable = rocketParams.mtvecWritable
val mulDivParams = rocketParams.mulDiv.getOrElse(MulDivParams()) // TODO ask andrew about this