riscv/rocket-chip
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Move microarchitecture-neutral params from Rocket to Core

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This makes some of the units more reusable.
This commit is contained in:
Andrew Waterman
2017-09-20 14:04:13 -07:00
parent 190d5c50d9
commit ab0821f25b
5 changed files with 18 additions and 12 deletions
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4
src/main/scala/rocket/PTW.scala
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@ -24,7 +24,7 @@ class PTWResp(implicit p: Parameters) extends CoreBundle()(p) {
}
class TLBPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasRocketCoreParameters {
with HasCoreParameters {
val req = Decoupled(new PTWReq)
val resp = Valid(new PTWResp).flip
val ptbr = new PTBR().asInput
@ -37,7 +37,7 @@ class PTWPerfEvents extends Bundle {
}
class DatapathPTWIO(implicit p: Parameters) extends CoreBundle()(p)
with HasRocketCoreParameters {
with HasCoreParameters {
val ptbr = new PTBR().asInput
val sfence = Valid(new SFenceReq).flip
val status = new MStatus().asInput