riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Move microarchitecture-neutral params from Rocket to Core

Browse Source 
This makes some of the units more reusable.
This commit is contained in:
Andrew Waterman
2017-09-20 14:04:13 -07:00
parent 190d5c50d9
commit ab0821f25b
5 changed files with 18 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/rocket/CSR.scala
View File

@@ -63,7 +63,7 @@ class DCSR extends Bundle {
}
class MIP(implicit p: Parameters) extends CoreBundle()(p)
with HasRocketCoreParameters {
with HasCoreParameters {
val lip = Vec(coreParams.nLocalInterrupts, Bool())
val zero2 = Bool()
val debug = Bool() // keep in sync with CSR.debugIntCause
@@ -144,7 +144,7 @@ object CSR
}
class PerfCounterIO(implicit p: Parameters) extends CoreBundle
with HasRocketCoreParameters {
with HasCoreParameters {
val eventSel = UInt(OUTPUT, xLen)
val inc = UInt(INPUT, log2Ceil(1+retireWidth))
}
@@ -161,7 +161,7 @@ class TracedInstruction(implicit p: Parameters) extends CoreBundle {
}
class CSRFileIO(implicit p: Parameters) extends CoreBundle
with HasRocketCoreParameters {
with HasCoreParameters {
val interrupts = new TileInterrupts().asInput
val hartid = UInt(INPUT, hartIdLen)
val rw = new Bundle {
@@ -207,7 +207,7 @@ class CSRFileIO(implicit p: Parameters) extends CoreBundle
}
class CSRFile(perfEventSets: EventSets = new EventSets(Seq()))(implicit p: Parameters) extends CoreModule()(p)
with HasRocketCoreParameters {
with HasCoreParameters {
val io = new CSRFileIO
val reset_mstatus = Wire(init=new MStatus().fromBits(0))