From a999c055edb9b4d8ce1566401ec29716f1cc5ed2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 11 Sep 2014 01:46:42 -0700 Subject: [PATCH] Don't take an interrupt when EX stage PC is invalid It was possible to take an interrupt on the instruction in the shadow of a short forward branch. EPC would thus get the wrong value, and so a wrong-path instruction would be executed upon return from interrupt. h/t Yunsup --- rocket/src/main/scala/dpath.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/dpath.scala b/rocket/src/main/scala/dpath.scala index 84a0a400..24e9c428 100644 --- a/rocket/src/main/scala/dpath.scala +++ b/rocket/src/main/scala/dpath.scala @@ -240,7 +240,7 @@ class Datapath extends Module Mux(io.ctrl.mem_branch && io.ctrl.mem_br_taken, imm(IMM_SB, mem_reg_inst), Mux(!io.ctrl.mem_jalr && !io.ctrl.mem_branch, imm(IMM_UJ, mem_reg_inst), SInt(4))) val mem_npc = Mux(io.ctrl.mem_jalr, Cat(vaSign(mem_reg_wdata, mem_reg_wdata), mem_reg_wdata(params(VAddrBits)-1,0)), mem_br_target) - io.ctrl.mem_misprediction := mem_npc != Mux(io.ctrl.ex_valid, ex_reg_pc, id_pc) + io.ctrl.mem_misprediction := mem_npc != ex_reg_pc || !io.ctrl.ex_valid io.ctrl.mem_rs1_ra := mem_reg_inst(19,15) === 1 val mem_int_wdata = Mux(io.ctrl.mem_jalr, mem_br_target, mem_reg_wdata)