riscv/rocket-chip
1
0
Fork 0
Code Releases Activity

Chisel3 compatibility: use more concrete types

Browse Source
This commit is contained in:
Andrew Waterman
2016-01-12 15:30:26 -08:00
parent c81745eb8e
commit a953ff384a
2 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
uncore/src/main/scala/cache.scala
View File

@@ -80,7 +80,7 @@ class PseudoLRU(n: Int)
def access(way: UInt) { def access(way: UInt) {
state_reg := get_next_state(state_reg,way) state_reg := get_next_state(state_reg,way)
} }
def get_next_state(state: Bits, way: UInt) = { def get_next_state(state: UInt, way: UInt) = {
var next_state = state var next_state = state
var idx = UInt(1,1) var idx = UInt(1,1)
for (i <- log2Up(n)-1 to 0 by -1) { for (i <- log2Up(n)-1 to 0 by -1) {

2
uncore/src/main/scala/util.scala
View File

@@ -18,7 +18,7 @@ object MuxBundle {
mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b)) mapping.reverse.foldLeft(default)((b, a) => Mux(a._1, a._2, b))
} }
def apply[S <: Data, T <: Data] (key: S, default: T, mapping: Seq[(S, T)]): T = { def apply[T <: Data] (key: UInt, default: T, mapping: Seq[(UInt, T)]): T = {
apply(default, mapping.map{ case (a, b) => (a === key, b) }) apply(default, mapping.map{ case (a, b) => (a === key, b) })
} }
} }