riscv/rocket-chip
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pbus: clarify that we are adding buffers when attaching to sbus

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Henry Cook 2017-09-01 18:18:13 -07:00 committed by Wesley W. Terpstra
parent 8fc4d78c84
commit a902e15987
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/coreplex/PeripheryBus.scala
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@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
val pbus = new PeripheryBus(pbusParams) val pbus = new PeripheryBus(pbusParams)
// The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 1) pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1)
} }

4
src/main/scala/coreplex/SystemBus.scala
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@ -37,8 +37,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
def toSplitSlaves: TLOutwardNode = outwardSplitNode def toSplitSlaves: TLOutwardNode = outwardSplitNode
def toPeripheryBus(nBuffers: Int): TLOutwardNode = { def toPeripheryBus(addBuffers: Int): TLOutwardNode = {
val (in, out) = bufferChain(nBuffers, name = Some("pbus")) val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
in := pbus_fixer.node in := pbus_fixer.node
out out
} }