diff --git a/src/main/scala/coreplex/PeripheryBus.scala b/src/main/scala/coreplex/PeripheryBus.scala
index 7e51691e..7cbbdb56 100644
--- a/src/main/scala/coreplex/PeripheryBus.scala
+++ b/src/main/scala/coreplex/PeripheryBus.scala
@@ -48,5 +48,5 @@ trait HasPeripheryBus extends HasSystemBus {
   val pbus = new PeripheryBus(pbusParams)
 
   // The peripheryBus hangs off of systemBus; here we convert TL-UH -> TL-UL
-  pbus.fromSystemBus := sbus.toPeripheryBus(nBuffers = 1)
+  pbus.fromSystemBus := sbus.toPeripheryBus(addBuffers = 1)
 }
diff --git a/src/main/scala/coreplex/SystemBus.scala b/src/main/scala/coreplex/SystemBus.scala
index f3022731..35cfb1c6 100644
--- a/src/main/scala/coreplex/SystemBus.scala
+++ b/src/main/scala/coreplex/SystemBus.scala
@@ -37,8 +37,8 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
 
   def toSplitSlaves: TLOutwardNode = outwardSplitNode
 
-  def toPeripheryBus(nBuffers: Int): TLOutwardNode = {
-    val (in, out) = bufferChain(nBuffers, name = Some("pbus"))
+  def toPeripheryBus(addBuffers: Int): TLOutwardNode = {
+    val (in, out) = bufferChain(addBuffers, name = Some("pbus"))
     in := pbus_fixer.node
     out
   }