riscv/rocket-chip
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Separate I$ parity error from miss signal

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Handle parity errors with a pipeline flush rather than a faster
frontend replay, reducing a critical path.
This commit is contained in:
Andrew Waterman
2017-08-04 00:37:13 -07:00
parent 06a831310b
commit a45997d03f
2 changed files with 4 additions and 2 deletions
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src/main/scala/rocket/Frontend.scala
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@ -149,7 +149,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer)
fq.io.enq.bits.data := icache.io.resp.bits.data
fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes))
fq.io.enq.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
fq.io.enq.bits.replay := icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt
fq.io.enq.bits.btb.valid := s2_btb_resp_valid
fq.io.enq.bits.btb.bits := s2_btb_resp_bits
fq.io.enq.bits.xcpt := s2_tlb_resp