From a45997d03f0bcf6d51f02ff7772e8073fec12046 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 4 Aug 2017 00:37:13 -0700 Subject: [PATCH] Separate I$ parity error from miss signal Handle parity errors with a pipeline flush rather than a faster frontend replay, reducing a critical path. --- src/main/scala/rocket/Frontend.scala | 2 +- src/main/scala/rocket/ICache.scala | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/Frontend.scala b/src/main/scala/rocket/Frontend.scala index b4f873a9..a5b30900 100644 --- a/src/main/scala/rocket/Frontend.scala +++ b/src/main/scala/rocket/Frontend.scala @@ -149,7 +149,7 @@ class FrontendModule(outer: Frontend) extends LazyModuleImp(outer) fq.io.enq.bits.data := icache.io.resp.bits.data fq.io.enq.bits.mask := UInt((1 << fetchWidth)-1) << s2_pc.extract(log2Ceil(fetchWidth)+log2Ceil(coreInstBytes)-1, log2Ceil(coreInstBytes)) - fq.io.enq.bits.replay := icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt + fq.io.enq.bits.replay := icache.io.resp.bits.replay || icache.io.s2_kill && !icache.io.resp.valid && !s2_xcpt fq.io.enq.bits.btb.valid := s2_btb_resp_valid fq.io.enq.bits.btb.bits := s2_btb_resp_bits fq.io.enq.bits.xcpt := s2_tlb_resp diff --git a/src/main/scala/rocket/ICache.scala b/src/main/scala/rocket/ICache.scala index d41321aa..330a7133 100644 --- a/src/main/scala/rocket/ICache.scala +++ b/src/main/scala/rocket/ICache.scala @@ -63,6 +63,7 @@ class ICache(val icacheParams: ICacheParams, val hartid: Int)(implicit p: Parame class ICacheResp(outer: ICache) extends Bundle { val data = UInt(width = outer.icacheParams.fetchBytes*8) + val replay = Bool() val ae = Bool() override def cloneType = new ICacheResp(outer).asInstanceOf[this.type] @@ -259,7 +260,8 @@ class ICacheModule(outer: ICache) extends LazyModuleImp(outer) io.resp.bits.data := s2_data_decoded.uncorrected io.resp.bits.ae := s2_tl_error - io.resp.valid := s2_valid && s2_hit && !s2_disparity + io.resp.bits.replay := s2_disparity + io.resp.valid := s2_valid && s2_hit tl_in.map { tl => val respValid = RegInit(false.B)