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Merge pull request #260 from ucb-bar/w1ToClear

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W1 to clear
This commit is contained in:
Henry Cook 2016-09-08 14:27:03 -07:00 committed by GitHub
commit a44fff5d93
2 changed files with 10 additions and 4 deletions
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2
src/main/scala/uncore/tilelink2/Bundles.scala
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@ -165,7 +165,7 @@ final class TLBundleD(params: TLBundleParameters)
final class TLBundleE(params: TLBundleParameters) final class TLBundleE(params: TLBundleParameters)
extends TLBundleBase(params) with TLChannel extends TLBundleBase(params) with TLChannel
{ {
val sink = UInt(width = params.sourceBits) // to val sink = UInt(width = params.sinkBits) // to
} }
class TLBundle(params: TLBundleParameters) extends TLBundleBase(params) class TLBundle(params: TLBundleParameters) extends TLBundleBase(params)

12
src/main/scala/uncore/tilelink2/RegField.scala
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@ -56,7 +56,7 @@ object RegWriteFn
}) })
// write to a DecoupledIO (only safe if there is a consistent sink draining data) // write to a DecoupledIO (only safe if there is a consistent sink draining data)
implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready })
// updates a register // updates a register (or adds a mux to a wire)
implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; Bool(true) }) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; Bool(true) })
// noop // noop
implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { Bool(true) }) implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { Bool(true) })
@ -73,8 +73,14 @@ object RegField
type Map = (Int, Seq[RegField]) type Map = (Int, Seq[RegField])
def apply(n: Int) : RegField = apply(n, (), ()) def apply(n: Int) : RegField = apply(n, (), ())
def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw)
def R(n: Int, r: RegReadFn) : RegField = apply(n, r, ()) def r(n: Int, r: RegReadFn) : RegField = apply(n, r, ())
def W(n: Int, w: RegWriteFn) : RegField = apply(n, (), w) def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w)
// This RegField allows 'set' to set bits in 'reg'.
// and to clear bits when the bus writes bits of value 1.
// Setting takes priority over clearing.
def w1ToClear(n: Int, reg: UInt, set: UInt): RegField =
RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) }))
} }
trait HasRegMap trait HasRegMap