From 99b7e734cdf39d912ab62bef89ec299a52d71e47 Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 12:14:55 -0700 Subject: [PATCH 1/2] tilelink2 Bundles: fix wrong sink width! --- src/main/scala/uncore/tilelink2/Bundles.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/uncore/tilelink2/Bundles.scala b/src/main/scala/uncore/tilelink2/Bundles.scala index 1548a4f3..5698b4f8 100644 --- a/src/main/scala/uncore/tilelink2/Bundles.scala +++ b/src/main/scala/uncore/tilelink2/Bundles.scala @@ -165,7 +165,7 @@ final class TLBundleD(params: TLBundleParameters) final class TLBundleE(params: TLBundleParameters) extends TLBundleBase(params) with TLChannel { - val sink = UInt(width = params.sourceBits) // to + val sink = UInt(width = params.sinkBits) // to } class TLBundle(params: TLBundleParameters) extends TLBundleBase(params) From 60a503dc2f14c12dbcf9507b7b82b1b155df2e0f Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Thu, 8 Sep 2016 13:46:56 -0700 Subject: [PATCH 2/2] tilelink2 RegField: add a w1ToClear RegField --- src/main/scala/uncore/tilelink2/RegField.scala | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/src/main/scala/uncore/tilelink2/RegField.scala b/src/main/scala/uncore/tilelink2/RegField.scala index 444a3c62..32a65c0d 100644 --- a/src/main/scala/uncore/tilelink2/RegField.scala +++ b/src/main/scala/uncore/tilelink2/RegField.scala @@ -56,7 +56,7 @@ object RegWriteFn }) // write to a DecoupledIO (only safe if there is a consistent sink draining data) implicit def apply(x: DecoupledIO[UInt]): RegWriteFn = RegWriteFn((valid, data) => { x.valid := valid; x.bits := data; x.ready }) - // updates a register + // updates a register (or adds a mux to a wire) implicit def apply(x: UInt): RegWriteFn = RegWriteFn((valid, data) => { when (valid) { x := data }; Bool(true) }) // noop implicit def apply(x: Unit): RegWriteFn = RegWriteFn((valid, data) => { Bool(true) }) @@ -73,8 +73,14 @@ object RegField type Map = (Int, Seq[RegField]) def apply(n: Int) : RegField = apply(n, (), ()) def apply(n: Int, rw: UInt) : RegField = apply(n, rw, rw) - def R(n: Int, r: RegReadFn) : RegField = apply(n, r, ()) - def W(n: Int, w: RegWriteFn) : RegField = apply(n, (), w) + def r(n: Int, r: RegReadFn) : RegField = apply(n, r, ()) + def w(n: Int, w: RegWriteFn) : RegField = apply(n, (), w) + + // This RegField allows 'set' to set bits in 'reg'. + // and to clear bits when the bus writes bits of value 1. + // Setting takes priority over clearing. + def w1ToClear(n: Int, reg: UInt, set: UInt): RegField = + RegField(n, reg, RegWriteFn((valid, data) => { reg := ~(~reg | Mux(valid, data, UInt(0))) | set; Bool(true) })) } trait HasRegMap