riscv/rocket-chip
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Update to new privileged ISA

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Andrew Waterman
2013-11-25 04:44:55 -08:00
parent 9e6e5adeba
commit a43cf9d688
7 changed files with 7 additions and 7 deletions
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2
src/main/scala/RocketChip.scala
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@@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf
val mem_backup = new ioMemSerialized(htif_width)
val mem_backup_en = Bool(INPUT)
}
val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif

2
src/main/scala/fpga.scala
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@@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit
val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip
val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput
}
val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR))
val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR))
val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif))
val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput)
outmemsys.io.incoherent := incoherentWithHtif