From a43cf9d68896a6e05b772c4d8a6dcab21709f44b Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 25 Nov 2013 04:44:55 -0800 Subject: [PATCH] Update to new privileged ISA --- chisel | 2 +- riscv-tests | 2 +- riscv-tools | 2 +- rocket | 2 +- src/main/scala/RocketChip.scala | 2 +- src/main/scala/fpga.scala | 2 +- uncore | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/chisel b/chisel index 4483d414..8dc0a8e6 160000 --- a/chisel +++ b/chisel @@ -1 +1 @@ -Subproject commit 4483d41471e4cb8e77b61f3f13255f4d59425d61 +Subproject commit 8dc0a8e6954bc4b40e5004c451bd12020c2ae0cb diff --git a/riscv-tests b/riscv-tests index fdf5e6f9..b374fd10 160000 --- a/riscv-tests +++ b/riscv-tests @@ -1 +1 @@ -Subproject commit fdf5e6f97d53722d7ec44c4591f1ab740a092808 +Subproject commit b374fd10b2b36124bb6813211a7ec690e1fa8350 diff --git a/riscv-tools b/riscv-tools index e5307451..20ff67d5 160000 --- a/riscv-tools +++ b/riscv-tools @@ -1 +1 @@ -Subproject commit e5307451589e339c56e54e869bdb1d74c6cb8e90 +Subproject commit 20ff67d56c3b505b99e531d48954c2c292a2fa99 diff --git a/rocket b/rocket index 80c4fb65..ba63ecb7 160000 --- a/rocket +++ b/rocket @@ -1 +1 @@ -Subproject commit 80c4fb65f40917b076576a30b574bdd4a0126251 +Subproject commit ba63ecb7cf3d2d2d871f35225ea89ba3141b8dae diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index b1df61c0..90cccf9c 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -157,7 +157,7 @@ class Uncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit conf val mem_backup = new ioMemSerialized(htif_width) val mem_backup_en = Bool(INPUT) } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new OuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/src/main/scala/fpga.scala b/src/main/scala/fpga.scala index 3aab9d29..e491caba 100644 --- a/src/main/scala/fpga.scala +++ b/src/main/scala/fpga.scala @@ -45,7 +45,7 @@ class FPGAUncore(htif_width: Int, tileList: Seq[ClientCoherenceAgent])(implicit val htif = Vec.fill(conf.nTiles){new HTIFIO(conf.nTiles)}.flip val incoherent = Vec.fill(conf.nTiles){Bool()}.asInput } - val htif = Module(new HTIF(htif_width, PCR.RESET, conf.nSCR)) + val htif = Module(new HTIF(htif_width, CSRs.reset, conf.nSCR)) val outmemsys = Module(new FPGAOuterMemorySystem(htif_width, tileList :+ htif)) val incoherentWithHtif = (io.incoherent :+ Bool(true).asInput) outmemsys.io.incoherent := incoherentWithHtif diff --git a/uncore b/uncore index ac4a5373..2a21e843 160000 --- a/uncore +++ b/uncore @@ -1 +1 @@ -Subproject commit ac4a5373c69c04a003bebe54fb7eca7387a43e4d +Subproject commit 2a21e8435a0b58ca588bfda0ab11b54e08efe3bd