DescribedReg: fix some imports

2018-03-06 11:02:10 -08:00
parent 8856953905
commit a3d99e5ba2
1 changed files with 1 additions and 0 deletions
--- a/src/main/scala/regmapper/DescribedReg.scala
+++ b/src/main/scala/regmapper/DescribedReg.scala
@@ -4,6 +4,7 @@ package freechips.rocketchip.regmapper
 import Chisel._
 import chisel3.experimental._
 import chisel3.{Input, Output}
+import freechips.rocketchip.util.{AsyncResetRegVec, SimpleRegIO}

 object DescribedReg {
  import freechips.rocketchip.regmapper.RegFieldAccessType._