40 lines
1.1 KiB
Scala
40 lines
1.1 KiB
Scala
// See LICENSE for license details.
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package freechips.rocketchip.regmapper
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import Chisel._
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import chisel3.experimental._
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import chisel3.{Input, Output}
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import freechips.rocketchip.util.{AsyncResetRegVec, SimpleRegIO}
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object DescribedReg {
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import freechips.rocketchip.regmapper.RegFieldAccessType._
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def apply[T <: Data](
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gen: => T,
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name: String,
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desc: String,
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reset: Option[T],
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access: RegFieldAccessType = RW,
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enumerations: Map[BigInt, (String, String)] = Map()): (T, RegFieldDesc) = {
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val rdesc = RegFieldDesc(name, desc, None, None,
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access, reset.map{_.litValue}, enumerations)
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val reg = reset.map{i => RegInit(i)}.getOrElse(Reg(gen))
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reg.suggestName(name + "_reg")
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(reg, rdesc)
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}
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def async(
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width: Int,
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name: String,
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desc: String,
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reset: Int,
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access: RegFieldAccessType = RW,
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enumerations: Map[BigInt, (String, String)] = Map()): (SimpleRegIO, RegFieldDesc) = {
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val rdesc = RegFieldDesc(name, desc, None, None,
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access, Some(reset), enumerations)
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val reg = Module(new AsyncResetRegVec(w = width, init = reset))
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reg.suggestName(name + "_reg")
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(reg.io, rdesc)
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}
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}
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