From a3d99e5ba21adaa6b0126acee18f803194b8144b Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Tue, 6 Mar 2018 11:02:10 -0800
Subject: [PATCH] DescribedReg: fix some imports

---
 src/main/scala/regmapper/DescribedReg.scala | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/main/scala/regmapper/DescribedReg.scala b/src/main/scala/regmapper/DescribedReg.scala
index da0d81a2..59be4a27 100644
--- a/src/main/scala/regmapper/DescribedReg.scala
+++ b/src/main/scala/regmapper/DescribedReg.scala
@@ -4,6 +4,7 @@ package freechips.rocketchip.regmapper
 import Chisel._
 import chisel3.experimental._
 import chisel3.{Input, Output}
+import freechips.rocketchip.util.{AsyncResetRegVec, SimpleRegIO}
 
 object DescribedReg {
   import freechips.rocketchip.regmapper.RegFieldAccessType._