riscv/rocket-chip
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fix merging of same xact ID puts/gets

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This commit is contained in:
Howard Mao 2016-07-04 17:00:03 -07:00
parent 51f7bf1511
commit a35388bc27
3 changed files with 6 additions and 3 deletions
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2
uncore/src/main/scala/agents/Broadcast.scala
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@ -142,7 +142,7 @@ class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
can_alloc = Bool(false), can_alloc = Bool(false),
next = s_inner_probe) next = s_inner_probe)
io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact_multibeat
// Track which clients yet need to be probed and make Probe message // Track which clients yet need to be probed and make Probe message
// If a writeback occurs, we can forward its data via the buffer, // If a writeback occurs, we can forward its data via the buffer,

3
uncore/src/main/scala/agents/Cache.scala
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@ -848,7 +848,8 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters)
can_alloc = Bool(true), can_alloc = Bool(true),
next = s_meta_read) next = s_meta_read)
io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact io.inner.acquire.ready := state === s_idle || iacq_can_merge ||
iacq_same_xact_multibeat
// Begin a transaction by getting the current block metadata // Begin a transaction by getting the current block metadata
// Defined here because of Chisel default wire demands, used in s_meta_resp // Defined here because of Chisel default wire demands, used in s_meta_resp

4
uncore/src/main/scala/agents/Trackers.scala
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@ -416,15 +416,17 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
(xact_iacq.client_xact_id === io.iacq().client_xact_id) && (xact_iacq.client_xact_id === io.iacq().client_xact_id) &&
(xact_iacq.client_id === io.iacq().client_id) && (xact_iacq.client_id === io.iacq().client_id) &&
pending_ignt pending_ignt
def iacq_same_xact_multibeat = iacq_same_xact && io.iacq().hasMultibeatData()
def iacq_can_merge: Bool def iacq_can_merge: Bool
def iacq_is_allocating: Bool = state === s_idle && io.alloc.iacq.should && io.inner.acquire.valid def iacq_is_allocating: Bool = state === s_idle && io.alloc.iacq.should && io.inner.acquire.valid
def iacq_is_merging: Bool = (iacq_can_merge || iacq_same_xact) && io.inner.acquire.valid def iacq_is_merging: Bool = (iacq_can_merge || iacq_same_xact) && io.inner.acquire.valid
def innerAcquire(can_alloc: Bool, next: UInt) { def innerAcquire(can_alloc: Bool, next: UInt) {
val iacq_matches_head = iacq_same_xact && xact_iacq.addr_beat === io.iacq().addr_beat
// Enqueue some metadata information that we'll use to make coherence updates with later // Enqueue some metadata information that we'll use to make coherence updates with later
ignt_q.io.enq.valid := iacq_is_allocating || ignt_q.io.enq.valid := iacq_is_allocating ||
(!iacq_same_xact && pending_ignt && (!iacq_matches_head && pending_ignt &&
io.inner.acquire.fire() && io.iacq().first()) io.inner.acquire.fire() && io.iacq().first())
ignt_q.io.enq.bits := io.iacq() ignt_q.io.enq.bits := io.iacq()