diff --git a/uncore/src/main/scala/agents/Broadcast.scala b/uncore/src/main/scala/agents/Broadcast.scala
index 6c466a92..0922fa89 100644
--- a/uncore/src/main/scala/agents/Broadcast.scala
+++ b/uncore/src/main/scala/agents/Broadcast.scala
@@ -142,7 +142,7 @@ class BufferedBroadcastAcquireTracker(trackerId: Int)(implicit p: Parameters)
     can_alloc = Bool(false),
     next = s_inner_probe)
 
-  io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact
+  io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact_multibeat
 
   // Track which clients yet need to be probed and make Probe message
   // If a writeback occurs, we can forward its data via the buffer,
diff --git a/uncore/src/main/scala/agents/Cache.scala b/uncore/src/main/scala/agents/Cache.scala
index 9adbf49c..109658cf 100644
--- a/uncore/src/main/scala/agents/Cache.scala
+++ b/uncore/src/main/scala/agents/Cache.scala
@@ -848,7 +848,8 @@ class CacheAcquireTracker(trackerId: Int)(implicit p: Parameters)
     can_alloc = Bool(true),
     next = s_meta_read)
 
-  io.inner.acquire.ready := state === s_idle || iacq_can_merge || iacq_same_xact
+  io.inner.acquire.ready := state === s_idle || iacq_can_merge ||
+                            iacq_same_xact_multibeat
 
   // Begin a transaction by getting the current block metadata
   // Defined here because of Chisel default wire demands, used in s_meta_resp
diff --git a/uncore/src/main/scala/agents/Trackers.scala b/uncore/src/main/scala/agents/Trackers.scala
index 9881d35d..71c96f40 100644
--- a/uncore/src/main/scala/agents/Trackers.scala
+++ b/uncore/src/main/scala/agents/Trackers.scala
@@ -416,15 +416,17 @@ trait AcceptsInnerAcquires extends HasAcquireMetadataBuffer
     (xact_iacq.client_xact_id === io.iacq().client_xact_id) &&
       (xact_iacq.client_id === io.iacq().client_id) &&
       pending_ignt
+  def iacq_same_xact_multibeat = iacq_same_xact && io.iacq().hasMultibeatData()
   def iacq_can_merge: Bool
   def iacq_is_allocating: Bool = state === s_idle && io.alloc.iacq.should && io.inner.acquire.valid
   def iacq_is_merging: Bool = (iacq_can_merge || iacq_same_xact) && io.inner.acquire.valid
 
   def innerAcquire(can_alloc: Bool, next: UInt) {
+    val iacq_matches_head = iacq_same_xact && xact_iacq.addr_beat === io.iacq().addr_beat
 
     // Enqueue some metadata information that we'll use to make coherence updates with later
     ignt_q.io.enq.valid := iacq_is_allocating ||
-                           (!iacq_same_xact && pending_ignt &&
+                           (!iacq_matches_head && pending_ignt &&
                              io.inner.acquire.fire() && io.iacq().first())
     ignt_q.io.enq.bits := io.iacq()