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Add firrtl and verilog Makefile targets to vsim

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This commit is contained in:
jackkoenig
2016-09-14 17:33:39 -07:00
committed by Howard Mao
parent cde104b3fa
commit a304695ffd
1 changed files with 5 additions and 0 deletions
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5
vsim/Makefrag-verilog
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@@ -5,6 +5,11 @@
# files.
.SECONDARY: $(generated_dir)/$(MODEL).$(CONFIG).fir
firrtl: $(generated_dir)/$(MODEL).$(CONFIG).fir
verilog: $(generated_dir)/$(MODEL).$(CONFIG).v
.PHONY: firrtl verilog
$(generated_dir)/%.$(CONFIG).fir $(generated_dir)/%.$(CONFIG).d $(generated_dir)/%.prm: $(chisel_srcs) $(bootrom_img)
mkdir -p $(dir $@)
cd $(base_dir) && $(SBT) "run $(generated_dir) $(PROJECT) $(notdir $*) $(CFG_PROJECT) $(CONFIG)"